FAN53526_17 datasheet(13/22 Pages) ONSEMI

Part #	FAN53526

Description	3.0 A, 2.4 MHz, Digitally Programmable TinyBuck Regulator

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Manufacturer	ONSEMI [ON Semiconductor]

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FAN53526

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13

this point, the high−side switch turns off, preventing high

currents from causing damage. 16 consecutive current limit

cycles in current limit

, cause the regulator to shut down and

stay off for about 1700

ms before attempting a restart.

Thermal Shutdown

When the die temperature increases, due to a high load

condition and/or high ambient temperature, the output

switching is disabled until the die temperature falls

sufficiently. The junction temperature at which the thermal

shutdown activates is nominally 150

°C with a 17°C

hysteresis.

Monitor Register (Reg05)

The Monitor register indicates of the regulation state of

the IC. If the IC is enabled and is regulating, its value is

(1000 0001).

I2C Interface

The serial interface is compatible with Standard, Fast,

Fast Plus, and HS Mode I2C Bus

R specifications. The SCL

line is an input and its SDA line is a bi−directional

open−drain output; it can only pull down the bus when

active. The SDA line only pulls LOW during data reads and

when signaling ACK. All data is shifted in MSB (bit 7) first.

I2C Slave Address

In hex notation, the slave address assumes a 0 LS Bit. The

hex slave address is C0 for all options except

FAN53526UC168X, which has a hex slave address of C2.

Table 12. I2C SLAVE ADDRESS

Hex

Bits

7

6

5

4

3

2

1

0

C0

1

0

C2

1

0

1

Other slave addresses can be assigned. Contact an On

Semiconductor representative.

Bus Timing

As shown in Figure 18 data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow sufficient time for the data to set up before

the next SCL rising edge.

SCL

tSU

tH

SDA

Data change allowed

Figure 18. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in Figure 19.

SCL

tHD;STA

SDA

Slave Address

MS Bit

Figure 19. START Bit

A transaction ends with a STOP condition, defined as

SDA transitioning from 0 to 1 with SCL high, as shown in

Figure 20.

SCL

SDA

Slave Releases

Master Drives

ACK(0) or

NACK(1)

t

HD;STO

Figure 20. STOP Bit

During a read from the FAN53526, the master issues a

REPEATED START after sending the register address and

before resending the slave address. The REPEATED

START is a 1 to 0 transition on SDA while SCL is HIGH, as

shown in Figure 21

.

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