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CYW20707 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CYW20707 Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 51 page Document Number: 002-14792 Rev. *H Page 6 of 51 PRELIMINARY CYW20707 1.2 Microprocessor Unit The CYW20707 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI). The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code. The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the internal ROM. External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an external serial flash memory. 1.2.1 NVRAM Configuration Data and Storage NVRAM contains configuration information about the customer application, including the following: ■ Fractional-N information ■ BD_ADDR ■ UART baud rate ■ SDP service record ■ File system information used for code, code patches, or data. The CYW20707 can use SPI Flash or I2C EEPROM/serial flash for NVRAM storage. 1.2.2 One-Time Programmable Memory The CYW20707 includes 2 Kbytes of one-time programmable (OTP) memory allow manufacturing customization and to avoid the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after the CYW20707 boots and is ready for host transport communication. Note: The OTP is disabled internally for the 36-Pin WLBGA package. The OTP contents are limited to: ■ Parameters required prior to downloading the user configuration to RAM. ■ Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key). |
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