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CYW4354XKWBG Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CYW4354XKWBG Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 165 page Document Number: 002-14809 Rev. *J Page 10 of 165 CYW4354 2. Power Supplies and Power Management 2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4354. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, WLAN, and FM functions in embedded designs. A single VBAT (3.0V to 5.25V DC max.) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW4354. Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband. The CYW4354 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 (which is a low-power linear regulator supplied by the system VIO supply) provides the CYW4354 with all the voltages it requires, further reducing leakage currents. 2.2 CYW4354 PMU Features ■ VBAT to 1.35Vout (600 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (600 mA maximum) LDO3P3 ■ VBAT to 3.3Vout (150 mA maximum) LDO3P3_B ■ VBAT to 2.5V out (70 mA maximum) BTLDO2P5 ■ 1.35V to 1.2Vout (150 mA maximum) LNLDO ■ 1.35V to 1.2Vout (300 mA maximum) CLDO with bypass mode for deep-sleep ■ Additional internal LDOs (not externally accessible) Figure 3 on page 11 illustrates the typical power topology for the CYW4354. The shaded areas are internal to the CYW4354. |
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