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CY15V104QSN Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY15V104QSN Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 90 page  PRELIMINARY CY15B104QSN CY15V104QSN Document Number: 002-18293 Rev. *E Page 8 of 90 Serial Clock (SCK) The serial clock is generated by the SPI master and the commu- nication is synchronized with this clock after CS goes LOW. The CY15x104QSN enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first Most Significant Bit (MSB) of an SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. Data Transmission (SI/SO) The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as Master-Out-Slave-In (MOSI) and SO is referred to as Master-In-Slave-Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. The CY15x104QSN has two separate pins for SI and SO, which can be connected with the master as shown in Figure 3. When in dual or quad I/O modes, these pins are configured as I/O pins. Figure 4 shows such a system interface with a QSPI port. Figure 3. System Configuration with SPI Port Figure 4. System Configuration with QSPI Port Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission. The 4-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only 19 bits, the five bits, which are fed in are ignored by the device. Although these five bits are ‘don’t care’, Cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY15x104QSN uses the standard opcodes (refer to Table 25 on page 20) for memory accesses. Invalid Opcode If a reserved opcode is received, the opcode may internally trigger unintended operation and start driving the I/O pin(s) with a non-deterministic data output. Hence, all opcodes under the reserved category should be avoided to transmit over SI pin when CY15x104QSN chip select CS is LOW. Instruction Instruction is the combination of the Opcode, address, mode and/or dummy bytes/cycles used to access the memory and registers Mode Bits The Mode byte is applicable for all write and read commands that support Execute-In-Place (XIP). The XIP is a method of executing the program (code) directly from an external memory rather than copying or shadowing the code into RAM. When the XIP is set for a write or read command, the device stays in XIP mode after the command cycle is terminated (CS toggles HIGH) so that the subsequent command cycle with CS LOW directly starts with the Address phase (Opcode phase is skipped). When in XIP, the device executes the same operation as in previous cycle. To initiate a new operation while in XIP, for example to switch from memory write to memory read or vice versa, the device should first exit the XIP for the current command cycle and initiate the next command cycle with Opcode phase. Opcodes with the Mode phase only support the XIP. See Table 25 on page 20 for the list of opcodes that require Mode phase. Following the opcode and 3-byte address cycles, the mode byte 0xAX (X don’t care bits) or 0xA5 (depending on the opcode) transmitted during the Mode phase keeps the device in XIP for the next command cycle. The XIP must be set during every command cycle to remain in XIP for the next command cycle. Any other value than 0xAX or 0xA5 (!0xAX or !0xA5) transmitted during the Mode phase will exit the XIP for the current operation. In this case, the next command cycle must always start with the Opcode phase to start the same operation or a new operation. Depending upon the SPI mode and the interface type, the number of clocks to transmit the mode byte will vary from two clocks (QPI, SDR) to eight clocks (SPI, SDR). SPI Hostcontroller or SPI Master SCK MOSI MISO CS1 CS2 GPIO1 GPIO 2 SCK (I/O0) SI (I/O1) SO RESET (I/O3) WP (I/O2) CY15X104QSN CS SCK (I/O0) SI (I/O1) SO RESET (I/O3) WP (I/O2) CY15X104QSN CS Optional connection; leave floating if not used QSPI Hostcontroller or QSPI Master SCK I/O0 I/O1 CS1 CS2 I/O2 I/O3 SCK (I/O0) SI (I/O1) SO RESET (I/O3) WP (I/O2) CY15X104QSN CS SCK (I/O0) SI (I/O1) SO RESET (I/O3) WP (I/O2) CY15X104QSN CS |
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