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DAT-15R5A-SP Datasheet(PDF) 5 Page - Mini-Circuits

Part No. DAT-15R5A-SP
Description  Digital Step Attenuator
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Maker  MINI [Mini-Circuits]
Homepage  http://www.minicircuits.com
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DAT-15R5A-SP Datasheet(HTML) 5 Page - Mini-Circuits

   
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Digital Step Attenuator
DAT-15R5A-SP+
Page 5 of 8
Mini-Circuits®
www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 sales@minicircuits.com
The serial interface is a 5-bit serial in, parallel-out shift register buffered by a transparent latch.
It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift
register control the attenuator. When LE is brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as
data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data.
The timing for this operation is defined by
Figure 2 (Serial Interface Timing Diagram) and Table 2 (Serial
Interface AC Characteristics).
Simplified Schematic
Figure 2: Serial interface Timing Diagram
The DAT-15R5A-SP+ serial interface consists of 5 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
State
C8
C4
C2
C1
C0.5
Reference
0
0
0
0
0
0.5 (dB)
0
0
0
0
1
1 (dB)
0
0
0
1
0
2 (dB)
0
0
1
0
0
4 (dB)
0
1
0
0
0
8 (dB)
1
0
0
0
0
15.5 (dB)
1
1
1
1
1
Note: Not all 32 possible combinations of C0.5 - C8 are shown
in table
LE
Clock
Data
MSB
LSB
t
LESUP
t
SDSUP tSDHLD
t
LEPW
Table 2. Serial Interface AC Characteristics
Symbol
Parameter
Min.
Max.
Units
f
clk
Serial data clock
frequency (Note 1)
10
MHz
t
clkH
Serial clock HIGH time
30
ns
t
clkL
Serial clock LOW time
30
ns
t
LESUP
LE set-up time after last
clock falling edge
10
ns
t
LEPW
LE minimum pulse
width
30
ns
t
SDSUP
Serial data set-up time
before clock rising edge
10
ns
t
SDHLD
Serial data hold time
after clock falling edge
10
ns
Note 1. fclk verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10MHz to verify fclk speci-
fication.
Digital Serial Control
RF Input
8dB
4dB
2dB
1dB
0.5dB
RF Out


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