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DAT-15R5A-PN Datasheet(PDF) 5 Page - Mini-Circuits

Part No. DAT-15R5A-PN
Description  Digital Step Attenuator
Download  8 Pages
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Maker  MINI [Mini-Circuits]
Homepage  http://www.minicircuits.com
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DAT-15R5A-PN Datasheet(HTML) 5 Page - Mini-Circuits

   
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Digital Step Attenuator
DAT-15R5A-PN+
Page 5 of 8
Mini-Circuits®
www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 sales@minicircuits.com
The parallel interface timing requirements are defined by Figure 2 (Parallel Interface Timing Diagram) and
Table 2 (Parallel Interface AC Characteristics), and switching speed.
For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW (per Figure 2) to latch new attenuation state into device.
For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation
state control values will change device state to new attenuation. Direct mode is ideal for manual control of
the device (using hardwire, switches, or jumpers).
Simplified Schematic
Figure 2: Parallel Interface Timing Diagram
The DAT-15R5A-PN+ parallel interface consists of 5 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
State
C8
C4
C2
C1
C0.5
Reference
0
0
0
0
0
0.5 (dB)
0
0
0
0
1
1 (dB)
0
0
0
1
0
2 (dB)
0
0
1
0
0
4 (dB)
0
1
0
0
0
8 (dB)
1
0
0
0
0
15.5 (dB)
1
1
1
1
1
Note: Not all 32 possible combinations of C0.5 - C8 are shown
in table
Table 2. Parallel Interface AC Characteristics
Symbol
Parameter
Min.
Max.
Units
t
LEPW
LE minimum pulse width
10
ns
t
PDSUP
Data set-up time before
clock rising edge of LE
10
ns
t
PDHLD
Data hold time
after clock falling edge of LE
10
ns
t
PDSUP
t
PDHLD
Parallel Data
C16:C0.5
LE
t
LEPW
RF Input
8dB
4dB
2dB
1dB
0.5dB
Parallel Control
Control Logic Interface
Latch Enable
RF Out


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