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CYW134SOXCT Datasheet(PDF) 2 Page - Silicon Laboratories |
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CYW134SOXCT Datasheet(HTML) 2 Page - Silicon Laboratories |
2 / 11 page W134 ........................ Document #: 38-07426 Rev. *C Page 2 of 11 Pin Definitions Pin Name No. Type Description REFCLK 2 I Reference Clock Input. Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). PCLKM 6 I Phase Detector Input. The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. SYNCLKN 7 I Phase Detector Input. The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. STOPB 11 I Clock Output Enable. When this input is driven to active LOW, it disables the differential Rambus Channel clocks. PWRDNB 12 I Active LOW Power-down. When this input is driven to active LOW, it disables the differ- ential Rambus Channel clocks and places the W134M/W134S in power-down mode. MULT 0:1 15, 14 I PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK. CLK, CLKB 20, 18 O Complementary Output Clock. Differential Rambus Channel clock outputs. S0, S1 24, 23 I Mode Control Input. These inputs control the operating mode of the W134M/W134S. NC 19 – No Connect VDDIR 1 RefV Reference for REFCLK. Voltage reference for input reference clock. VDDIPD 10 RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB. VDD 3, 9, 16, 22 P Power Connection. Power supply for core logic and output buffers. Connected to 3.3V supply. GND 4, 5, 8, 13, 17, 21 G Ground Connection. Connect all ground pins to the common system ground plane. MULT1 0 1 1 0 MULT0 0 0 1 1 W134M PLL/REFCLK 4.5 6 8 5.333 W134S PLL/REFCLK 4 6 8 5.333 S1 0 1 0 1 S0 0 0 1 1 MODE Normal Output Enable Test Bypass Test W134M/W134S Refclk W133 PLL Phase Align D 4 DLL RAC RMC M N Gear Ratio Logic Pclk Busclk Synclk W158 W159 W161 W167 Figure 1. DDLL System Architecture CY2210 |
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