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CYW256OXC Datasheet(PDF) 5 Page - Silicon Laboratories |
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CYW256OXC Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 8 page W256 ..........................Document #: 38-07256 Rev. *C Page 5 of 7 t3d DDR Rising Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) 0.5 1.50 V/ns t4d DDR Falling Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) 0.5 1.50 V/ns t5 Output to Output Skew[4] All outputs equally loaded 100 ps t6 Output t4o Output Skew for SDRAM[2] All outputs equally loaded 150 ps t7 SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns 5 10 ns t8 SDRAM Buffer LLProp. Delay[4] Input edge greater than 1 V/ns 5 10 ns Switching Waveforms Switching Characteristics[4] Parameter Name Test Conditions Min. Typ. Max. Unit Duty Cycle Timing t1 t2 All Outputs Rise/Fall Time OUTPUT t3 3.3V 0V 0.4V 2.4V 2.4V 0.4V t4 Output-Output Skew t5 OUTPUT OUTPUT SDRAM Buffer HH and LL Propagation Delay t6 INPUT OUTPUT t7 1.5V 1.5V Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns. |
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