Rev AB January 16, 2011

Document Number: SP-AP-0198

Page 9 of 16

SL38160-17AH

SL38160-23AH

Table 1. Audio Clock Frequency Settings (pin 11)

Audio

Clk

(MHz)

Register Byte# DEC and Bit [7:0] HEX Setting

Byte 40 Byte 41 Byte 42 Byte 43

Byte129

8.1920

04

02

1F

18

81

11.2896

0C

45

DE

78

81

12.2880

04

01

F6

38

81

24.57603

04

01

F5

18

81

16.9344

09

33

E9

D8

81

18.4320

04

01

F5

78

81

36.8640

04

01

F4

B8

81

16.3840

08

03

85

D8

81

22.5792

0C

45

DD

38

81

49.1520

08

03

84

98

81

33.8688

06

21

F5

38

81

73.7280

04

01

F4

58

81

Table 2. Digital Television Video Clock Frequency Settings (pin 9)

Video Clk

(MHz)

Register Byte# (DEC) and Bit [7:0] HEX, Setting

Byte17

Byte18

Byte19

Byte22

Byte48

Byte49

Byte 50

Byte51 Byte128

13.50000

07

80

AB

C6

04

00

7E

C7

34

27.00000

07

80

AB

C6

04

00

5E

C7

34

54.00000

07

80

AB

C6

04

00

4E

C7

34

74.17582

3

05

80

AB

DE

1F

6D

86

C7

36

74.25000

07

00

AB

C6

05

80

86

C7

34

148.35170

05

80

AB

DE

1F

6D

82

C7

36

148.50000

07

80

AB

C6

05

80

82

C7

34