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SPL505YC256BT Datasheet(PDF) 6 Page - Silicon Laboratories |
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SPL505YC256BT Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 27 page SPL505YC25 ......................Document #: 001-03543 Rev *E Page 6 of 27 7 HW FS_C CPU Frequency Select Bit, set by HW 6 HW FS_B CPU Frequency Select Bit, set by HW 5 HW FS_A CPU Frequency Select Bit, set by HW 4 0 iAMT_EN Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1 3 0 RESERVED RESERVED 2 0 SRC_MAIN_SEL Select source for SRC clock, 0 = SRC_MAIN = PLL1, PLL3_CFB Table applies 1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply 1 0 SATA_SEL Select source of SATA clock 0 = SATA SRC_MAIN, 1= SATA PLL2 0 1 PD_Restore Save Config. In powerdown 0 = Config. Cleared, 1 = Config. Saved Byte 0: Control Register 0 Byte 1: Control Register 1 Bit @Pup Name Description 7 0 SRC0_SEL Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96 6 0 PLL1_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 Bit 4:1 only apply when SRC_SEL=0 0000 = PLL3 Disable Default PLL3 OFF, SRC1 = SRC_MAIN 0001 = 100 MHz 0.5% SSC Stby PLL3 ON, SRC1 = SRC_MAIN 0010 = 100 MHz 0.5% SSC Only SRC1 sourced from PLL3 0011 = 100 MHz 1.0% SSC Only SRC1 sourced from PLL3 0100 = 100 MHz 1.5% SSC Only SRC1 sourced from PLL3 0101 = 100 MHz 2.0% SSC Only SRC1 sourced from PLL3 0110 = RESERVED 0111 = RESERVED 1000 = RESERVED Note: SE clocks required to be 1001 = RESERVED enabled through Byte 8 Bit1:0 1010 = RESERVED 1011 = 27MHz_NSS on SE1 and SE2 1100 = 25MHz on SE1 and SE2 1101 = 25MHz on SE1 and SE2 Disabled (set whenPCI3/CFB0 is set high to config to HW mode 3) 1110 = RESERVED 1111 = RESERVED 3 0 PLL3_CFB2 2 0 PLL3_CFB1 1 1 PLL3_CFB0 0 1 PCI_SEL Select PCI Clock source from PLL1 or SRC_MAIN 0 = PLL1, 1 = SRC_MAIN Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 USB_OE Output enable for USB 0 = Output Disabled, 1 = Output Enabled 5 1 PCIF0_OE Output enable for PCIF0 0 = Output Disabled, 1 = Output Enabled 4 1 PCI4_OE Output enable for PCI4, 0 = Output Disabled, 1 = Output Enabled 3 1 PCI3_OE Output enable for PCI3, 0 = Output Disabled, 1 = Output Enabled |
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