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SL28748ELC Datasheet(PDF) 5 Page - Silicon Laboratories |
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SL28748ELC Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 19 page SL28748 DOC#: SP-AP-0017 (Rev. AA) Page 5 of 19 Control Registers Byte 0: Control Register 0 Bit @Pup Name Description 7 HW FS CPU Frequency Select Bit, set by HW 0 = 133MHz, 1= 100MHz 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 iAMT_EN iAMT Enable 0 = Legacy Mode, 1 = iAMT Enabled 3 0 RESERVED RESERVED 2 0 SRC_Main_SEL Select source for SRC clock 0 = SRC_MAIN = PLL1, PLL3_CFG Table applies 1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply 1 0 SATA_SEL Select source of SATA clock 0 = SATA = SRC_MAIN, 1= SATA = PLL4 0 1 PD_Restore Save configuration when PD# is asserted 0 = Config. cleared, 1 = Config. saved Byte 1: Control Register 1 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0) See Table 4 on page 9 for Configuration. 3 0 PLL3_CFB2 2 1 PLL3_CFB1 1 0 PLL3_CFB0 0 1 RESERVED RESERVED Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED |
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