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SL28748 Datasheet(PDF) 11 Page - Silicon Laboratories |
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SL28748 Datasheet(HTML) 11 Page - Silicon Laboratories |
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11 / 19 page  SL28748 DOC#: SP-AP-0017 (Rev. AA) Page 11 of 19 CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable are stopped within two to six CPU clock periods after sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. CPU_STP# Deassertion The deassertion of the CPU_STP# signal causes all stopped CPU outputs to resume normal operation in a synchronous manner. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Figure 3. CKPWRGD Timing Diagram CPU_STP# CPUT CPUC Figure 4. CPU_STP# Assertion Waveform CPU_STP# CPUT CPUC CPUT Internal Tdrive_CPU_STP#,10 ns>200 mV CPUC Internal Figure 5. CPU_STP# Deassertion Waveform |
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