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SL28506BZC-2T Datasheet(PDF) 2 Page - Silicon Laboratories |
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SL28506BZC-2T Datasheet(HTML) 2 Page - Silicon Laboratories |
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2 / 27 page  SL28506-2 .........................DOC #: SP-AP-0021 (Rev AB) Page 2 of 27 56 TSSOP Pin Definition Pin No. Name Type Description 1 PCI0/OE#_0/2_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or SRC2. (Default PCI0, 33MHz clock) 2 VDD_PCI PWR 3.3V Power supply for PCI PLL. 3 PCI1/OE#_1/4_B I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or SRC4. (Default PCI1, 33MHz clock) 4 PCI2/TME I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) 5 PCI3/CFG0 I/O, SE, PD 3.3V tolerant input for CPU frequency selection/3.3V 33MHz clock. (Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and Vih_PCI3/CFG0 specifications). 6 PCI4/SRC5_EN I/O, SE 3.3V tolerant input to enable SRC5/3.3V, 33MHz clock. (Sampled on the CKPWRGD assertion) 1 = SRC5, 0 = CPU_STP# 7 PCIF/ITP_EN I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/3.3V, 33MHz clock. (Sampled on the CKPWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 8 VSS_PCI GND Ground for outputs. 9 VDD_48 PWR 3.3V Power supply for outputs and PLL. 10 USB_48/FSA I/O 3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) 11 VSS_48 GND Ground for outputs. 12 VDD_IO PWR 0.7V Power supply for outputs. 13 SRC0/DOT96 O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 14 SRC0#/DOT96# O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 15 VSS_IO GND Ground for PLL2. 16 VDD_PLL3 PWR 3.3V Power supply for PLL3 17 SRC1/LCD100/SE1 O, DIF, SE 100MHz Differential serial reference clocks/100MHz LCD video clock/SE1 clocks. (Default SRC1, 100MHz clock) 18 SRC1#/LCD100#/SE2 O, DIF, SE 100MHz Differential serial reference clocks/100MHz LCD video clock/SE2 clocks. (Default SRC1, 100MHz clock) 19 VSS_PLL3 GND Ground for PLL3. 20 VDD_PLL3_IO PWR IO Power supply for PLL3 outputs. 21 SRC2/SATA O, DIF 100MHz Differential serial reference clocks. 22 SRC2#/SATA# O, DIF 100MHz Differential serial reference clocks. 23 VSS_SRC GND Ground for outputs. 24 SRC3/OE#_0/2_B I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock) 25 SRC3#OE#_1/4_B I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock) |
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