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SL28506 Datasheet(PDF) 10 Page - Silicon Laboratories |
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SL28506 Datasheet(HTML) 10 Page - Silicon Laboratories |
10 / 29 page SL28506 .......................DOC #: SP-AP-0021 (Rev AA) Page 10 of 28 3 1 PCI_DIV_EN PCI Divider Enabled 0 = PCI Divider disabled, 1 = PCI Divider enabled 2 1 CPU_DIV_EN CPU Divider Enabled 0 = CPU Divider disabled, 1 = CPU Divider enabled 1 1 CPU1_STP_CRTL Allow control of CPU1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU0_STP_CRTL Allow control of CPU0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Byte 10: Control Register 10 (continued) Bit @Pup Name Description Byte 11: Control Register 11 Bit @Pup Name Description 7 HW PCI3_CFG1 6 HW PCI3_CFG0 5 0 25MHz_EN_SE1 25MHz Output Enabled applies to Powerdown / M1 (Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3) 0 = 25MHz disabled in Powerdown / M1 1 = 25MHz enabled in Powerdown / M1; Sticky 1 4 1 RESERVED RESERVED 3 0 CPU2_AMT_EN 2 1 CPU1_AMT_EN 1 1 PCI-E_GEN2 PCI-E_Gen2 Compliant (Read Only) 0 = non Gen2, 1= Gen2 Compliant 0 1 CPU2_STP_CRTL Allow control of CPU2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Output SSC Output SSC 00 x Low 0 -Def CPU / SRC / PCI33 Dow n USB NA 01 x Mid 1 CPU Dow n USB NA 10 0 High 2 CPU Center USB NA PLL2 CFG [1:0] PCI3/ CGF0 Mode PLL1 PCI2/T ME PCIF0/ITP_EN AMT_EN CPU2_AMT_EN CPU1_AMT_EN Description x1 0 0 Reserved x 1 0 1 CPU1 = M1 Clock 1 1 1 0 CPU2 - M1 Clock 1 1 1 1 CPU1 and CPU2 = M1 Clock Byte 12: Byte Count Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 BC5 Byte count 4 0 BC4 Byte count 3 1 BC3 Byte count 2 1 BC2 Byte count 1 0 BC1 Byte count 0 1 BC0 Byte count |
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