3.1.9 Locked Mode

Once lock is achieved, the Si5380 will generate output clocks that are both frequency and phase locked to the input clock. The DSPLL

will provide jitter attenuation of the input clock using the selected DSPLL loop bandwidth. At this point, any XTAL frequency drift inside

of the loop bandwidth will not affect the output frequencies. When lock is achieved, the LOLb pin will output a logic high level. The LOL

status bit and LOLb status pin will also indicate that the DSPLL is locked. See the 3.4.6 LOL Detection section for more details on LOLb

detection time.

3.1.10 Holdover Mode

The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are

available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance

of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical

frequency data while the DSPLL is locked to a valid clock input. The final averaged holdover frequency value is calculated from a pro-

grammable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the

figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data

that may be corrupt just before the input clock failure.

Figure 3.3. Programmable Holdover Window

Programmable delay

Clock Failure

and Entry into

Holdover

time

0s

Historical Frequency Data Collected

Programmable historical data window

used to determine the final holdover value

120s

1s,10s, 30s, 60s

30ms, 60ms, 1s,10s, 30s, 60s

When entering holdover, the DSPLL will pull the output clock frequencies referred to the calculated averaged holdover frequency. While

in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB

pins. If a new clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input

clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the new input clock. This

pull-in process is glitchless and its rate is controlled by the DSPLL bandwidth and the Fastlock bandwidth. These options are register

programmable.

The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference be-

tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-

ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40

values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit

from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on

ramped input switching, see 3.3.5 Ramped Input Switching.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

Si5380 Rev D Data Sheet

Functional Description

silabs.com | Smart. Connected. Energy-friendly.

Rev. 1.0 | 7