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Si5332C Datasheet(PDF) 11 Page - Silicon Laboratories |
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Si5332C Datasheet(HTML) 11 Page - Silicon Laboratories |
11 / 59 page 3.5 Outputs The Si5332 supports up to 12 differential output drivers. Each output can be independently configured as a differential pair or as dual LVCMOS outputs. The 8-output and 12-output devices feature banks of outputs, with each bank sharing a common VDDO. Table 3.1. Clock Outputs Package Maximum Outputs 32-QFN 6 Differential, 12 LVCMOS 40-QFN 8 Differential, 16 LVCMOS 48-QFN 12 Differential, 24 LVCMOS The output stage is different for each of the three versions of Si5332. • The 6-output device features individual VDDO pins for each clock output. Each clock output can be sourced from MultiSynth0, Multi- Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX. • The 8-output device includes four clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0, Multi- Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The remaining four clock outputs are divided into Bank A and Bank B. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The outputs in each of the two Banks share a common VDDO pin. • The 12-output device includes two clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0, Multi- Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The remaining ten clock outputs are divided into Bank A, Bank B, Bank C, and Bank D. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The outputs in each of the four Banks share a common VDDO pin. Utilizing the reference clock enables a fan-out buffer function from an input clock source to any bank of outputs. Individual output Integer output dividers (R) allow the generation of additional synchronous frequencies. These integer dividers are con- figurable as divide by 1 (default) through 63. 3.5.1 Output Signal Format The differential output swing and common mode voltage are both fully programmable and compatible with a wide variety of signal for- mats including HCSL, LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS drivers, enabling the device to support both differential and single-ended clock outputs. Output formats can be defined in ClockBuilder Pro or via the serial interface. Si5332 Data Sheet Functional Description silabs.com | Building a more connected world. Rev. 0.7 | 11 |
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