2.2.2 SPI Communication Transactions

SPI communication is performed using a four wire control interface. The four Si838x device pins utilized for SPI include:

• SCLK (input) the SPI clock

• NSS (input) active low device select

• MOSI (input) master-out-slave-in

• MISO (output) master-in-slave-out

Additionally, a fifth wire SDI_THRU (output) is provided as an Si838x device pin to facilitate daisy chaining.

An Si838x SPI communication packet is composed of three serial bytes. In this sequence, byte0 is the control byte, and specifies the

operation to be performed as well as the device to be selected in a daisy chain organization. The CID[3:0] field should be set to all

zeros by the SPI master in non-daisy-chained operation. Next, byte1 specifies the address of the internal Si838x SPI register to be

accessed. The final byte in the packet consists of either the data to be written to the addressed Si838x SPI register (using MOSI), or the

data read from the addressed Si838x SPI register (using MISO). Details of the SPI communication packet are presented in the following

figure for an Si838x SPI write transaction.

NSS

SCLK

MOSI

Control[7:0]

Address[7:0]

Data[7:0]

BRCT

1 - broadcast (write)

0 - only addressed part (write)

Ignored on reads

R/Wb

1 - read

0 - write

CTL[5:4]

Reserved (set to 0,0)

CID[3:0]

Daisy-chained part ID (0) is closest to the master

MOSI. Accomplished by decrementing the CID as

it passes through to the next Si838x device in the

daisy chain on SDI_THRU

Control Byte

7

6

5

4

3

2

1

0

BRCT R/Wb

0

0

CID[0] CID[1] CID[2] CID[3]

Address Byte

7

6

5

4

3

2

1

0

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

Data Byte

7

6

5

4

3

2

1

0

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Figure 2.2. SPI Communication Packet Structure, Write Operation and Control Byte Structure

The SPI master will provide the timing of the signals and framing of the communication packets for all Si838x SPI inputs: NSS, SCLK,

and MOSI. Data is communicated from the SPI master to the Si838x using the MOSI signal. The NSS and SCLK signals provide the

necessary control and timing reference allowing the Si838x to discern valid data on the MOSI signal. Data is returned to the SPI master

by the Si838x utilizing the MISO signal only during the final byte of a three byte SPI read communication packet. At all other times, the

MISO signal is tri-stated by the Si838x. Each of the eight bits for these three packets is captured by the Si838x on eight adjacent rising

edges of SCLK. Each frame of eight bits is composed within bounding periods where the device select, NSS, is deasserted. Upon the

reception of the eight bits within a byte transaction, the deassertion of NSS advances the byte counter within the internal Si838x SPI

state machine. Should the transmission of an eight bit packet be corrupted, either with the deassertion of NSS before the eighth rising

edge of SCLK, or with the absence of the deassertion of NSS after the eighth rising edge of SCLK, the internal SPI state machine may

become unsynchronized with the master SPI controller.

To re-establish SPI synchronization with the Si838x, the SPI master may, at any time, deassert the SPI device select signal NSS, and

force a clock cycle on SCLK. When unsynchronized, the rising edge of SCLK when NSS is deasserted (high) re-initializes the internal

SPI state machine. The Si838x will then treat the immediately following eight bit SPI transaction after NSS is once again asserted as

the first byte in a three byte SPI communication packet.

Any preceding communication packet will be abandoned by the Si838x at the point synchronization is lost, and the NSS signal is deas-

serted. This could occur at any point in the three byte sequence of a SPI communication packet. One should note that abandoning a

SPI write operation early, even during the last byte of the three byte SPI communication packet, will leave the destination register un-

changed. However, if the number of SCLK cycles exceeds eight during the last byte of the three byte SPI write packet, the destination

Si838x register may be corrupted. To remedy both of these situations, it is recommended that such a corrupted write operation be re-

peated immediately following resynchronization of the SPI interface.

Si838x Data Sheet

Functional Description

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