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Si8384PF-IU Datasheet(PDF) 5 Page - Silicon Laboratories

Part # Si8384PF-IU
Description  Bipolar Digital Field Inputs for PLCs and Industrial I/O Modules
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

Si8384PF-IU Datasheet(HTML) 5 Page - Silicon Laboratories

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2.2.3 SPI Read Operation
Referring to Figure 2.2 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 3, in a SPI read op-
eration the control byte will only have bit6 set to a 1 in a single Si838x device organization (no daisy-chaining). For the Si838x, bit7 (the
broadcast bit) is ignored during a read operation since only one device may be read at a time in either a single or daisy chained organi-
zation.
The second byte in the three byte read packet is provided by the SPI master to designate the address of the Si838x internal register to
be queried. If the read address provided does not correspond to a physically available Si838x internal register, all zeroes will be re-
turned as the read value by the Si838x.
The read data is provided during the final byte of the three byte read communication packet to the querying master SPI device utilizing
the Si838x’s MISO output, which remains tristated at all other times.
The SPI read operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
Control[7:0]
Address[7:0]
ReadData[7:0]
MISO
Figure 2.3. SPI Read Operation
2.2.4 SPI Write Operation
Again referring to Figure 2.2 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 3, in a SPI
write operation the control byte may optionally have bit7 (the broadcast bit) set to a 1. During a SPI write operation, the broadcast bit
forces all daisy-chained Si838x devices to update the designated internal SPI register with the supplied write data, regardless of the
Si838x device being addressed using the CID[3:0] field of the control word.
The second byte in the three byte write packet is provided by the SPI master to designate the address of the Si838x internal register to
be updated. If the write address provided does not correspond to a physically available Si838x internal register, no internal Si838x SPI
register update will occur.
The write data is provided by the SPI master during the final byte of the three byte write communication packet. The Si838x MISO
output remains tri-stated during the entire SPI write operation.
The SPI write operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
Control[7:0]
Address[7:0]
MISO
hiZ
WriteData[7:0]
Figure 2.4. SPI Write Operation
Si838x Data Sheet
Functional Description
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