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CY28551LFXC Datasheet(PDF) 9 Page - Silicon Laboratories

Part # CY28551LFXC
Description  Universal Clock Generator for Intel, VIA, and SIS짰
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28551LFXC Datasheet(HTML) 9 Page - Silicon Laboratories

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CY28551
....................... Document #: 001-05675 Rev. D Page 9 of 28
1
0
R
Vendor ID Bit 1
Vendor ID Bit 1
0
0
R
Vendor ID Bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Type
Name
Description
7
0
R/W
CR1_PCIEX7
PCIEX[T/C75 CLKREQ#A Control
1 = PCIEX [T/C]5 stoppable by CLKREQ#B pin
0 = Free running
6
0
R/W
CR1_PCIEX6
PCIEX[T/C]6 CLKREQ#A Control
1 = PCIEX [T/C]4 stoppable by CLKREQ#B pin
0 = Free running
5
0
R/W
CR1_PCIEX5
PCIEX[T/C]5 CLKREQ#B Control
1 = PCIEX [T/C]5 stoppable by CLKREQ#B pin
0 = Free running
4
0
R/W
CR1_PCIEX4
PCIEX[T/C]4 CLKREQ#B Control
1 = PCIEX [T/C]4 stoppable by CLKREQ#B pin
0 = Free running
3
0
R/W
RESERVED
RESERVED, Set = 0
2
0
R/W
RESERVED
RESERVED, Set = 0
1
0
R/W
RESERVED
RESERVED, Set = 0
0
0
R/W
RESERVED
RESERVED, Set = 0
Byte 7: Vendor ID (continued)
Bit
@Pup
Type
Name
Description
Byte 9: Control Register 9
Bit
@Pup
Type
Name
Description
7
0
R/W
DF3_N8
The DF3_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =11
6
0
R/W
DF2_N8
The DF2_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =10
5
0
R/W
DF1_N8
The DF1_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =01
4
0
R/W
RESERVED
RESERVED, Set = 0
3
0
R/W
RESERVED
RESERVED, Set = 0
2
1
R/W
SMSW_Bypass
Smooth switch Bypass
0 = Activate SMSW block
1 = Bypass and deactivate SMSW block.
1
0
R/W
SMSW_SEL
Smooth switch select
0 = Select CPU_PLL
1 = Select SRC_PLL
0
0
R/W
RESERVED
RESERVED, Set = 0


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