CY28508

........................ Document #: 38-07534 Rev. *F Page 5 of 13

Byte 3: Dial-a-Frequency Control Register N1 [default = 224.70 MHz, N = 86d, ODSEL = 1]

Bit

@Pup

Description

7

0

Reserved, set = 0.

61

N6, MSB

50

N5

41

N4

30

N3

21

N2

11

N1

00

N0, LSB

Byte 4: Dial-a-Frequency Control Register M1 [default = 224.70 MHz, M = 49d, ODSEL = 1]

Bit

@Pup

Description

7

1

Reserved, set = 1.

6

1

SWODSEL: Output divider select. 0 = /2, 1 = /3.

Changing the output divider causes large instantaneous changes in the CPU pulse width and

should only be changed before system operation is to occur.

5

1

M5 MSB.

41

M4

30

M3

20

M2

10

M1

0

1

M0, LSB.

Byte 5: Dial-a-Frequency Control Register N2 – Only Bit 7 is Used by the CY28508

Bit

@Pup

Description

7

0

UP/DN pulse width limit. During Smooth-Track, the bandwidth hence the slew rate is controlled through

limiting the pulse width of the UP/DN pulse outputs of the phase detector going to the charge pump. The

default is 0 = 20 ns and can be programmed to 1 = 40 ns, which will increase the slew rate.

6

0

Reserved, set = 0.

5

1

Reserved, set = 1.

4

1

Reserved, set = 1.

3

0

Reserved, set = 0.

2

0

Reserved, set = 0.

1

0

Reserved, set = 0.

0

0

Reserved, set = 0.

Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508

Bit

@Pup

Description

7

1

FSEL Control: 1 = HW FSEL, 0 = SW FSEL

6

1

SW FSEL: 0 = SW MN0 select, 1 = SW MN1 select. Only valid when B6b7 = 0.

5

1

Reserved, set = 1.

4

1

Reserved, set = 1.

3

0

Reserved, set = 0.

2

0

Reserved, set = 0.

1

0

Reserved, set = 0.

0

0

Reserved, set = 0.