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CY28508OXC Datasheet(PDF) 11 Page - Silicon Laboratories |
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CY28508OXC Datasheet(HTML) 11 Page - Silicon Laboratories |
11 / 14 page CY28508 ...................... Document #: 38-07534 Rev. *F Page 11 of 13 IDDR Power supply additional current for all 3.3V VDDs for loaded REF only Output is 14.31818 MHz with VCO running 666.6 MHz 810 mA IDD2A Power supply current for all 2.5V VDDs with three buffers enabled and loaded Output is 224.7 MHz with VCO running 666.6 MHz 180 225 mA IDD2B Power supply current for all 2.5V VDDs with two buffers enabled and loaded Output is 224.7 MHz with VCO running 666.6 MHz 124 155 mA IDD2C Power supply current for all 2.5V VDDs with one buffer enabled and loaded Output is 224.7 MHz with VCO running 666.6 MHz 70 90 mA IDD2D Power supply current for all 2.5V VDDs with all buffers disabled Output is 224.7 MHz with VCO running 666.6 MHz 710 mA AC Electrical Specifications Parameter Description Condition Min. Typ. Max. Unit Crystal TDC Xin Duty Cycle Measured at VDDX/2 45 55 % TPERIOD Xin Period Measured at VDDX/2. The VCO frequency must remain within its operating range. 52.4 69.841 87.3 ns REF Output TDC REF Duty Cycle Measured at 1.5V, 15-pF lumped load. 45 50 55 % TRISE/TFALL REF Rise and Fall Times Measured from 0.4V to 2.4V, 15-pF lumped load. 1 4 ns TCCJ REF Cycle to Cycle Jitter Measured at 1.5V, 15-pF lumped load. 1000 ps LOCK Output TFALL Lock Fall Time Measured from 2.4V to 0.4V, 10-pF lumped load and 10K pull-up. 0.5 2 ns CPU Outputs TDC CPUT/C Duty Cycle Measured at 0.62V at measuring point. See Figure 7. 45 50 55 % TRISE/TFALL CPUT/C Rise and Fall Times Measured from 0.3V to 0.9V. See Figure 7. 150 500 ps TSKEW CPUT/C to CPUT/C Clock Skew Measured at 0.62V at measuring point. See Figure 7. 100 ps TCCJ CPUT/C Cycle to Cycle Jitter Measured at 0.62V at measuring point. See Figure 7. 135 ps VDIF Differential Voltage Swing At load measuring point. See Figures 7 and 8. 1.24 1.5 VOX Crossing Point Voltage At load measuring point. See Figures 7 and 8. 0.4 0.62 0.9 V FVCO VCO Operating Frequency Over voltage, temperature and process 333 675 MHz TXS Power-on Hold Off Outputs will be as shown in Figure 6 1.2 ms Table 6. Slew Rate Settings Output Divider = /3 (Measured over 10 s) M N Range Typ. Max. Slew Rate (kHz/ S) Worst-Corner Max Slew Rate (kHz/ S) ICP B2b7 Ns B7b7 Variable ICP B8b7 49 43-65 55 100 x1 2048 1 49 65-86 75 140 x1 2048 or 1024 1 49 43-86 45 70 x1 2048 0 DC Electrical Specifications (continued) Parameter Description Condition Min. Typ. Max. Unit Table 7. Slew Rate Settings Output Divider = /2 (Measured over 10 s) M N Range Typ. Max. Slew Rate (kHz/ S) Worst-Corner Max Slew Rate (kHz/ S) ICP B2b7 Ns B7b7 Variable ICP B8b7 49 43-65 80 150 x1 2048 1 49 65-86 120 200 x1 2048 or 1024 1 49 43-86 65 100 x1 2048 0 |
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