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CY28508OXC Datasheet(PDF) 7 Page - Silicon Laboratories |
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CY28508OXC Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 14 page CY28508 ........................ Document #: 38-07534 Rev. *F Page 7 of 13 This circuitry is designed to present simultaneous M&N values to the VCO when writing to the I2C lines. If not for this delay in writing the N register value, the VCO would use a new N value and an old M value and would go to an indeterminate frequency until the next I2C byte was written. Crystal Recommendations The CY28508 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28508 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (CL). Figure 2 shows a typical crystal configuration using the two trim capacitors. An important clari- fication for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capaci- tance of the crystal. N Register M Register Byte N1 W rite FSEL Latch SMBus DAF-M1 SMBus DAF-N1 Byte M1 W rite Latch SMBus DAF-M0 SMBus DAF-N0 Byte M0 W rite Byte N0 W rite Figure 1. Dial-a-Frequency Register Switching and Synchronizer Circuitry Figure 2. Crystal Capacitive Clarification Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 50 ppm 50 ppm 5 ppm |
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