CY28447

........................ Document #: 38-07724 Rev *C Page 3 of 22

Frequency Select Pins (FSA, FSB, and FSC)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FSA, FSB, FSC inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled LOW by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FSA, FSB, and FSC input values. For all logic

levels of FSA, FSB, and FSC, VTT_PWRGD# employs a

one-shot functionality in that once a valid LOW on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FSA, FSB, and FSC transitions will be ignored, except in test

mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 2.

The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h)

.

39

VTT_PWRGD#/PD

I, PD

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FSA, FSB,

FSC, FCTSEL1, and ITP_SEL. After VTT_PWRGD# (active LOW) assertion, this

pin becomes a real-time input for asserting power down (active HIGH).

40

VDD_48

PWR

3.3V power supply for outputs.

41

48M/FSA

I/O

Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

42

VSS_48

GND

Ground for outputs.

43, 44

DOT96T/ 27M_NSS

DOT96C/ 27M_SS

O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output

Selected via FCTSEL1 at VTTPWRGD# assertion.

45

FSB/TEST_MODE

I

3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state

when in test mode

0 = Tri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

47, 48

SRC[T/C]0/

LCD100M[T/C]

O,DIF 100-MHz differential serial reference clock output / Differential 96/100-MHz

SS clock for flat-panel display

Selected via FCTSEL1 at VTTPWRGD# assertion.

Pin No.

Name

Type

Description

Table 1. Frequency Select Table FSA, FSB, and FSC[1]

FSC

FSB

FSA

CPU

SRC

PCIF/PCI

27MHz

REF0

DOT96

USB

1

0

1

100 MHz

100 MHz

33 MHz

27 MHz

14.318 MHz

96 MHz

48 MHz

0

0

1

133 MHz

100 MHz

33 MHz

27 MHz

14.318 MHz

96 MHz

48 MHz

0

1

1

166 MHz

100 MHz

33 MHz

27 MHz

14.318 MHz

96 MHz

48 MHz

0

1

0

200 MHz

100 MHz

33 MHz

27 MHz

14.318 MHz

96 MHz

48 MHz

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Note:

1. 27-MHz and 96-MHz can not be output at the same time.