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CY28353OC-2T Datasheet(PDF) 3 Page - Silicon Laboratories |
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CY28353OC-2T Datasheet(HTML) 3 Page - Silicon Laboratories |
3 / 9 page CY28353-2 .......................... Document #: 38-07372 Rev. *B Page 3 of 9 Zero Delay Buffer When used as a zero delay buffer the CY28353-2 will likely be in a nested clock tree application. For these applications the CY28353-2 offers a differential clock input pair as a PLL reference. The CY28353-2 then can lock onto the reference and translate with near zero delay to low skew outputs. For normal operation, the external feedback input, FBINT, is connected to the feedback output, FBOUTT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped low, the PLL is turned off and bypassed for test purposes. Power Management The individual output enable/disable control of the CY28353-2 allows the user to implement unique power management schemes into the design. Outputs are tri-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output pair (FBOUTT, FBOUTC) cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block r\ead operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1Start 1 Start 8:2 Slave address – 7 bits 8:2 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 Bits 18:11 Command Code – 8 Bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 28 Acknowledge from slave 27:21 Slave address – 7 bits 36:29 Data byte 1 – 8 bits 28 Read = 1 37 Acknowledge from slave 29 Acknowledge from slave 45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits 46 Acknowledge from slave 38 Acknowledge .... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits .... Data Byte N –8 bits 47 Acknowledge .... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits .... Stop 56 Acknowledge |
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