CY28353-2

.......................... Document #: 38-07372 Rev. *B Page 2 of 9

Pin Description [1]

Pin Number

Pin Name

I/O

Pin Description

Electrical Characteristics

8CLKINT

I

Complementary Clock Input.

LV Differential Input

9CLKINC

I

Complementary Clock Input.

21

FBINC

I

Feedback Clock Input. Connect to

FBOUTC for accessing the PLL.

Differential Input

20

FBINT

I

Feedback Clock Input. Connect to

FBOUTT for accessing the PLL.

2,4,13,17,24,26

CLKT(0:5)

O

Clock Outputs.

Differential Outputs

1,5,14,16,25,27

CLKC(0:5)

O

Clock Outputs.

19

FBOUTT

O

Feedback Clock Output. Connect to

FBINT for normal operation. A bypass

delay capacitor at this output will control

Input Reference/Output Clocks phase

relationships.

Differential Output

18

FBOUTC

O

Feedback Clock Output. Connect to

FBINC for normal operation. A bypass

delay capacitor at this output will control

Input Reference/Output Clocks phase

relationships.

7SCLK

I, PU Serial Clock Input. Clocks data at

SDATA into the internal register.

Data Input for the two-line serial

bus

22

SDATA

I/O,

PU

Serial Data Input. Input data is clocked

to the internal register to enable/disable

individual outputs. This provides flexi-

bility in power management.

Data Input and Output for the

two-line serial bus

3,12,23

VDD

2.5V Power Supply for Logic.

2.5V Nominal

10

AVDD

2.5V Power Supply for PLL.

2.5V Nominal

6,15,28

GND

Ground.

11

AGND

Analog Ground for PLL.

Function Table

Inputs

Outputs

PLL

VDDA

CLKINT

CLKINC

CLKT(0:5)[2]

CLKC(0:5)[2]

FBOUTT

FBOUTC

GND

L

H

L

H

L

H

BYPASSED/OFF

GND

H

L

H

L

H

L

BYPASSED/OFF

2.5V

L

H

L

H

L

H

On

2.5V

H

L

H

L

H

L

On

2.5V

< 20 MHz

< 20 MHz

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Off

Notes:

1. A bypass capacitor (0.1

F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their

high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.

2. Each output pair can be three-stated via the two-line serial interface.