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CY28346OCT Datasheet(PDF) 14 Page - Silicon Laboratories

Part No. CY28346OCT
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  SILABS [Silicon Laboratories]
Homepage  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28346OCT Datasheet(HTML) 14 Page - Silicon Laboratories

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CY28346
......................Document #: 38-07331 Rev. *C Page 14 of 19
Absolute Maximum Ratings[5]
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65
C to + 150C
Operating Temperature:.................................... 0
C to +85C
Maximum Power Supply:................................................ 3.5V
Current Accuracy[6]
Parameter
Conditions
Configuration
Load
Min.
Max.
Iout
VDD = nominal (3.30V)
M0 = 0 or 1 and Rr (see Table 1)
Nominal test load for given
configuration
–7%
Inom
+ 7%
Inom
Iout
VDD = 3.30 ± 5%
All combinations of M0 or 1 and Rr
(see Table 1)
Nominal test load for given
configuration
–12%
Inom
+ 12%
Inom
DC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IDD3.3V
Dynamic Supply Current
All frequencies at maximum values[7]
280
mA
IPD3.3V
Power-down Supply Current
PD# asserted
Note 8
mA
CIN
Input Pin Capacitance
5pF
COUT
Output Pin Capacitance
6pF
LPIN
Pin Inductance
7nH
CXTAL
Crystal Pin Capacitance
Measured from the XIN or XOUT pin to ground
30
36
42
pF
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Crystal
TDC
XIN Duty Cycle
47.5
52.5
47.5
52.5
47.5
52.5
47.5
52.5
%
9, 10, 11
TPERIOD
XIN period
69.84
71.0
69.84
71.0
69.84
71.0
69.84
71.0
ns
9, 12,
13, 10
VHIGH
XIN HIGH Voltage
0.7VDD
VDD
0.7VDD
VDD
0.7VDD
VDD
0.7VDD
VDD
V
VLOW
XIN LOW Voltage
0
0.3VDD
00.3VDD
00.3VDD
00.3VDD
V
TR / TF
XIN Rise and Fall Times
10.0
10.0
10.0
10.0
ns
14
TCCJ
XIN Cycle to Cycle Jitter
500
500
500
500
ps
12, 15,
10
CPU at 0.7V Timing
TDC
CPUT and CPUC Duty
Cycle
45
55
45
55
45
55
45
55
%
15, 16,
19
TPERIOD
CPUT and CPUC
Period
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
ns
15, 16,
19
TSKEW
Any CPU to CPU Clock
Skew
100
100
100
100
ps
12, 15,
16
Notes:
5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inom refers to the expected current based on the configuration of the device.
7. All outputs loaded as per maximum capacitive load table.
8. Absolute value = ((Programmed CPU Iref) × (2)) + 10 mA.
9. This parameter is measured as an average over 1
s duration, with a crystal center frequency of 14.31818 MHz.
10. When Xin is driven from an external clock source.
11. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
12. All outputs loaded as perTable 9 below.
13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
14. Measured between 0.2VDD and 0.7VDD.
15. This measurement is applicable with Spread ON or Spread OFF.
16. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V Measured from VOL = 0.175V to VOH = 0.525V.
17. Measured from VOL = 0.175V to VOH = 0.525V.
18. Determined as a fraction of 2*(Trise–Tfall)/ (Trise+Tfall).
19. Test load is Rta = 33.2
, Rd = 49.9.


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