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CY28346OCT Datasheet(PDF) 10 Page - Silicon Laboratories

Part No. CY28346OCT
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  SILABS [Silicon Laboratories]
Homepage  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28346OCT Datasheet(HTML) 10 Page - Silicon Laboratories

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CY28346
......................Document #: 38-07331 Rev. *C Page 10 of 19
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see
Figure 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
Table 7. Cypress Clock Power Management Truth Table
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable
CPUC
Non-Stop CPUT
Non-Stop CPUC
0
0
1
1
Running
Running
Running
Running
0
0
1
0
Iref x6
Iref x6
Running
Running
0
0
0
1
Iref x2
LOW
Iref x2
LOW
0
0
0
0
Iref x2
LOW
Iref x2
LOW
0
1
1
1
Running
Running
Running
Running
0
1
1
0
Hi-Z
Hi-Z
Running
Running
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
1
1
Running
Running
Running
Running
1
0
1
0
Iref x6
Iref x6
Running
Running
1
0
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
1
1
Running
Running
Running
Running
1
1
1
0
Hi-Z
Hi-Z
Running
Running
1
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform


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