Clock Synthesizer with Differential CPU Outputs

CY28346

........................ Document #: 38-07331 Rev. *C Page 1 of 19

400 West Cesar Chavez, Austin, TX 78701

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Features

specifications

• 3.3V power supply

• Three differential CPU clocks

• Ten copies of PCI clocks

• 5/6 copies of 3V66 clocks

• SMBus support with read-back capabilities

• Spread Spectrum electromagnetic interference (EMI)

reduction

• Dial-a-Frequency™ features

• Dial-a-dB™ features

• 56-pin TSSOP and SSOP packages

Table 1. Frequency Table[1]

S2

S1

S0

CPU (0:2)

3V66

66BUFF(0:2)/

3V66(0:4)

66IN/3V66–5

PCI_FPCI

REF

USB/

DOT

1

0

0

66M

66M

66IN

66-MHz clock input

66IN/2

14.318M

48M

1

0

1

100M

66M

66IN

66-MHz clock input

66IN/2

14.318M

48M

1

1

0

200M

66M

66IN

66-MHz clock input

66IN/2

14.318M

48M

1

1

1

133M

66M

66IN

66-MHZ clock input

66IN/2

14.318M

48M

0

0

0

66M

66M

66M

66M

33 M

14.318M

48M

0

0

1

100M

66M

66M

66M

33 M

14.318M

48M

0

1

0

200M

66M

66M

66M

33 M

14.318M

48M

0

1

1

133M

66M

66M

66M

33 M

14.318M

48M

M

0

0

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

M

0

1

TCLK/2

TCLK/4

TCLK/4

TCLK/4

TCLK/8

TCLK

TCLK/2

Note:

1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a

0 state will be latched into the device’s internal state register.

PLL1

PLL2

/2

WD

Logic

Power

Up Logic

XIN

XOUT

CPU_STP#

IREF

VSSIREF

S(0:2)

MULT0

VTT_PG#

PCI_STP#

PD#

SDATA

SCLK

VDDA

66B[0:2]/3V66[2:4]

48M DOT

48M USB

PCI_F(0:2)

PCI(0:6)

3V66_1/VCH

3V66_0

CPUC(0:2)

CPUT(0:2)

REF

66IN/3V66-5

I2C

Logic

VDD

XIN

XOUT

VSS

PCIF0

PCIF1

PCIF2

VDD

VSS

PCI0

PCI1

PCI2

PCI3

VDD

VSS

PCI4

PCI5

PCI6

VDD

VSS

66B0/3V66_2

66B1/3V66_3

66B2/3V66_4

66IN/3V66_5

PD#

VDDA

VSSA

VTT_PG#

REF

S1

S0

CPU_STP#

CPUT0

CPUC0

VDD

CPUT1

CPUC1

VSS

VDD

CPUT2

CPUC2

MULT0

IREF

VSSIREF

S2

48MUSB

48MDOT

VDD

VSS

3V66_1/VCH

PCI_STP#

3V66_0

VDD

VSS

SCLK

SDATA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Pin Configuration

Block Diagram