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CY28346OCT Datasheet(PDF) 6 Page - Silicon Laboratories |
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CY28346OCT Datasheet(HTML) 6 Page - Silicon Laboratories |
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6 / 19 page 
CY28346 ........................Document #: 38-07331 Rev. *C Page 6 of 19 Dial-a-Frequency Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Dial-a-dB Features SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Test and Measurement Set-up For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. Table 2. P Value S(1:0) P 0 0 32005333 0 1 48008000 1 0 96016000 1 1 64010667 Table 3. Spread Spectrum SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 0 0 1 Down +0.00, –0.50 0 1 0 Down +0.00, –0.75 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 1 1 1 Center +0.50, –1.50 M eas urem en t P oint 2p F CP U T M U L T SEL T PCB T PCB CP U C M easurem ent P o int 2p F Figure 1. 1.0V Test Load Termination CPUT MULTSEL T PCB T PCB CPUC Measurement Point 2pF Measurement Point 2pF VDD Figure 2. 0.7V Test Load Termination |
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