C9530

.......................Document #: 38-07033 Rev. *C Page 4 of 10

1

0

SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)

0

1

HWSEL

Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 = SMBus

Byte 0 bits 1-4, & 6

Table 4. Clarification Table for Byte0, bit 5

Byte0, bit6

Byte0, bit5

Description

0

0

Frequency generated from second PLL

0

1

Frequency generated from XIN

1

0

Spread @ –1.0%

1

1

Spread @ –0.5%

Table 5. Test Table

Test Function Clock

Outputs

CLKA

CLKB

REF

Frequency

XIN/6

XIN/4

XIN

Byte 1: A Bank and REF Clock Control Register

Bit

@Pup

Name

Description

71

Reserved

61

Reserved

5

1

REFEN

REF Output Enable

0 = Disable, 1= Enable

4

1

CLKA4 Output Enable

0 = Disable, 1= Enable

3

1

CLKA3 Output Enable

0 = Disable, 1= Enable

2

1

CLKA2 Output Enable

0 = Disable, 1= Enable

1

1

CLKA1 Output Enable

0 = Disable, 1= Enable

0

1

CLKA0 Output Enable

0 = Disable, 1= Enable

Byte 2: PCI Register

Bit

@Pup

Name

Description

71

Reserved

61

Reserved

51

Reserved

4

1

18

CLKB4 Output Enable

0 = Disable, 1= Enable

3

1

19

CLKB3 Output Enable

0 = Disable, 1= Enable

2

1

22

CLKB2 Output Enable

0 = Disable, 1= Enable

1

1

23

CLKB1 Output Enable

0 = Disable, 1= Enable

0

1

24

CLKB0 Output Enable

0 = Disable, 1= Enable

Byte 0: Function Select Register (continued)

Bit

@Pup

Name

Description