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DS26502 Datasheet(PDF) 2 Page - Maxim Integrated Products

Part # DS26502
Description  T1/E1/J1/64KCC BITS Element
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS26502 Datasheet(HTML) 2 Page - Maxim Integrated Products

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DS26502 T1/E1/J1/64KCC BITS Element
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TABLE OF CONTENTS
1.
FEATURES......................................................................................................................7
1.1
GENERAL ........................................................................................................................7
1.2
LINE INTERFACE...............................................................................................................7
1.3
JITTER ATTENUATOR (T1/E1 MODES ONLY) ......................................................................7
1.4
FRAMER/FORMATTER .......................................................................................................8
1.5
TEST AND DIAGNOSTICS ...................................................................................................8
1.6
CONTROL PORT ...............................................................................................................8
2.
SPECIFICATIONS COMPLIANCE ...................................................................................9
3.
BLOCK DIAGRAMS .......................................................................................................11
4.
PIN FUNCTION DESCRIPTION .....................................................................................14
4.1
TRANSMIT PLL...............................................................................................................14
4.2
TRANSMIT SIDE..............................................................................................................14
4.3
RECEIVE SIDE................................................................................................................15
4.4
CONTROLLER INTERFACE................................................................................................16
4.5
JTAG ...........................................................................................................................20
4.6
LINE INTERFACE.............................................................................................................20
4.7
POWER .........................................................................................................................21
5.
PINOUT...........................................................................................................................22
6.
HARDWARE CONTROLLER INTERFACE....................................................................25
6.1
TRANSMIT CLOCK SOURCE .............................................................................................25
6.2
INTERNAL TERMINATION..................................................................................................25
6.3
LINE BUILD-OUT.............................................................................................................26
6.4
RECEIVER OPERATING MODES........................................................................................26
6.5
TRANSMITTER OPERATING MODES ..................................................................................27
6.6
MCLK PRE-SCALER ......................................................................................................27
6.7
OTHER HARDWARE CONTROLLER MODE FEATURES .........................................................28
7.
PROCESSOR INTERFACE ............................................................................................29
7.1
PARALLEL PORT FUNCTIONAL DESCRIPTION.....................................................................29
7.2
SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION .................................................29
7.2.1 Clock Phase and Polarity .........................................................................................29
7.2.2 Bit Order...................................................................................................................29
7.2.3 Control Byte .............................................................................................................29
7.2.4 Burst Mode...............................................................................................................29
7.2.5 Register Writes.........................................................................................................30
7.2.6 Register Reads ........................................................................................................30
7.3
REGISTER MAP ..............................................................................................................31
7.3.1 Power-Up Sequence ................................................................................................33
7.3.2 Test Reset Register .................................................................................................33
7.3.3 Mode Configuration Register....................................................................................34
7.4
INTERRUPT HANDLING ....................................................................................................37
7.5
STATUS REGISTERS .......................................................................................................37
7.6
INFORMATION REGISTERS ...............................................................................................38


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