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DS90LV110AT Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DS90LV110AT
Description  1 to 10 LVDS Data/Clock Distributor with Failsafe
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90LV110AT Datasheet(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENT
I
CCD
Total Supply Current
R
L = 100
Ω,C
L = 5 pF, 200 MHz,
125
160
mA
EN = High
No Load, 200 MHz, EN = High
80
125
mA
I
CCZ
TRI-STATE Supply Current
EN = Low
15
29
mA
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All typical are given for VCC = +3.3V and TA = +25˚C, unless otherwise stated.
Note 3: VOS is defined as (VOH +VOL)/2.
Note 4: Only one output can be shorted at a time. Don’t exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
LHT
Output Low-to-High Transition Time, 20% to 80%, Figure 4
(Note 5)
390
550
ps
T
HLT
Output High-to-Low Transition Time, 80% to 20%, Figure 4
(Note 5)
390
550
ps
T
DJ
LVDS Data Jitter, Deterministic
(Peak-to-Peak)(Note 6)
V
ID = 300mV; PRBS=2
23-1 data;
V
CM = 1.2V at 400 Mbps (NRZ)
145
ps
T
RJ
LVDS Clock Jitter, Random (Note 6)
V
ID = 300mV; VCM = 1.2V
at 200 MHz clock
2.8
ps
T
PLHD
Propagation Low to High Delay, Figure 5
2.2
2.8
3.6
ns
T
PHLD
Propagation High to Low Delay, Figure 5
2.2
2.8
3.9
ns
T
SKEW
Pulse Skew |T
PLHD -TPHLD| (Note 5)
20
340
ps
T
CCS
Output Channel-to-Channel Skew, Figure 6 (Note 5)
35
91
ps
T
PHZ
Disable Time (Active to TRI-STATE) High to Z, Figure 1
3.0
6.0
ns
T
PLZ
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
1.8
6.0
ns
T
PZH
Enable Time (TRI-STATE to Active) Z to High, Figure 1
10.0
23.0
ns
T
PZL
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
7.0
23.0
ns
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6: The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a TDJ = 26ps and TRJ = 1.3 ps
www.national.com
3


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