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PLDC20G10B Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. PLDC20G10B
Description  CMOS Generic 24-Pin Reprogrammable Logic Device
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

PLDC20G10B Datasheet(HTML) 1 Page - Cypress Semiconductor

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USE ULTRA37000™ FOR
ALL NEW DESIGNS
CMOS Generic 24-Pin Reprogrammable
Logic Device
PLDC20G10B
PLDC20G10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-03010 Rev. *A
Revised April 20, 2004
Features
• Fast
— Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns
— Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns
•Low power
—ICC max.: 70 mA, commercial
—ICC max.: 100 mA, military
• Commercial and military temperature range
• User-programmable output cells
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or
product term
• Generic architecture to replace standard logic
functions including: 20L10, 20L8, 20R8, 20R6, 20R4,
12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE product term per output
• CMOS EPROM technology for reprogrammability
• Highly reliable
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
±10% power supply voltage and higher noise
immunity
Functional Description
Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
difference is in the location of the “no connect” or NC pins.
Logic Block Diagram
Pin Configurations
8
98
7
6
5
4
3
2
1
10
15
16
17
18
19
20
21
22
23
24
PROGRAMMABLE
AND ARRAY
I
I
II
II
I
I
CP/I
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
V CC
11
12
13
14
I
VSS
I/OE
8
OUTPUT
CELL
8
OUTPUT
CELL
I
I/O 9
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I
I
I
I
I
NC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
432
2827 26
I
I
I
I
I
I
1
1
I
I/O 2
I/O 3
I/O4
I/O5
I/O 6
I/O 7
NC
PLDC20G10
PLDC20G10B
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
NC
I
I
I
I
NC
1
NC
I/O 2
I/O3
I/O 4
I/O5
I/O 6
I/O7
NC
JEDEC PLCC
Top View
STD PLCC
Top View
LCC
Top View
I/O2
I/O3
I/O4
I/O5
I/O 6
I/O 7
NC
PLDC20G10
PLDC20G10B
CG7C323–A
CG7C323B–A
NC
[1]


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