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HT32F1653 Datasheet(PDF) 36 Page - Holtek Semiconductor Inc |
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HT32F1653 Datasheet(HTML) 36 Page - Holtek Semiconductor Inc |
36 / 46 page Rev. 1.00 36 of 46 �an�a�� ��� �01� 3�-bit ARM® Co�tex™-M3 MCU HT3�F16�3/HT3�F16�4 SAR ADC CI sample RI RS VS Figure 6 ADC Sampling Network Model The worst case occurs when the extremities of the input range (0V and VREF) are sampled consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following equation: I N I ADC S R C f R − < + ) 2 ln( 5 . 1 2 where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, Rs may be larger than the value indicated by the equation above. |
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