Digital Controlled Variable Gain Amplifier (DVGA)

DVGA1-242A+

Page 8 of 9

Notes

A. Performance and quality attributes and conditions not expressly stated in this specification document are intended to be excluded and do not form a part of this specification document.

B. Electrical specifications and performance data contained in this specification document are based on Mini-Circuit’s applicable established test performance criteria and measurement instructions.

C. The parts covered by this specification document are subject to Mini-Circuits standard limited warranty and terms and conditions (collectively, “Standard Terms”); Purchasers of this part are entitled

to the rights and benefits contained therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder, please visit Mini-Circuits’ website at www.minicircuits.com/MCLStore/terms.jsp

The DVGA1-242A+, uses a common 6-bit serial, as shown in Table 4: 6-Bit attenuator Serial Programming Register

Map. The first bit, the MSB, corresponds to the 16-dB Step and the last bit, the LSB, corresponds to the 0.5dB step.

The DVGA1-242A+ always assumes a specifiable attenuation setting on power-up, allowing a known attenuation state

to be established before an initial serial control word is provided. When the attenuator powers up, the six control bits

are set to whatever data is present on the six control inputs (C0.5 to C16). This allows any one of the 64 attenuation

settings to be specified as the power-up state.

Power-up Control Settings

Table 4. 6-Bit attenuator Serial Programming Register Map

B5

B4

B3

B2

B1

B0

C16

C8

C4

C2

C1

C0.5

MSB

(first in)

LSB

(last in)

Symbol

Parameter

Min.

Max.

Units

f

clk

Serial data clock

frequency (Note 1)

10

MHz

t

clkH

Serial clock HIGH time

30

ns

t

clkL

Serial clock LOW time

30

ns

t

LESUP

LE set-up time after last

clock falling edge

10

ns

t

LEPW

LE minimum pulse

width

30

ns

t

SDSUP

Serial data set-up time

before clock rising edge

10

ns

t

SDHLD

Serial data hold time

after clock falling edge

10

ns

Note 1. fclk verified during the functional pattern test. Serial programming

sections of the functional pattern are clocked at 10MHz to verify fclk speci-

fication.

LE

Clock

Data

MSB

LSB

t

LESUP

t

t

LEPW