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F280045PZS Datasheet(PDF) 7 Page - Texas Instruments |
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F280045PZS Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 217 page  7 TMS320F280049, TMS320F280049C TMS320F280048, TMS320F280048C, TMS320F280045 TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C www.ti.com SPRS945C – JANUARY 2017 – REVISED DECEMBER 2017 Submit Documentation Feedback Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C Revision History Copyright © 2017, Texas Instruments Incorporated 2 Revision History Changes from October 7, 2017 to December 15, 2017 (from B Revision (October 2017) to C Revision) Page • Global: TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045, TMS320F280041, TMS320F280041C, TMS320F280040, and TMS320F280040C are now fully qualified production devices. See Device and Development Support Tool Nomenclature. ............................................ 1 • Global: Removed STANDBY low-power mode. ................................................................................. 1 • Global: Removed TMS320F280049M and InstaSPIN-MOTION™. ........................................................... 1 • Section 1.1 (Features): Updated section. ......................................................................................... 1 • Section 1.3 (Description): Added paragraph about Embedded Real-Time Analysis and Diagnostic (ERAD) module. . 3 • Figure 4-4 (56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View)): Updated figure. ............................... 16 • Table 4-1 (Pin Attributes): Added "PAD" to "56 RSH" column of VSS. ...................................................... 17 • Table 4-4 (Power and Ground): Added "PAD" to "56 RSH" column of VSS. ............................................... 30 • Section 5 (Specifications): Updated ESD Ratings – Commercial. ............................................................ 54 • Section 5: Updated ESD Ratings – Automotive. ................................................................................ 54 • Section 5: Updated Recommended Operating Conditions. .................................................................... 54 • Section 5: Updated Electrical Characteristics .................................................................................. 54 • Figure 5-1 (Supply Voltages): Added figure. .................................................................................... 56 • Section 5.5 (Power Consumption Summary): Removed STANDBY low-power mode. .................................... 57 • Section 5.8.1.2 (Internal 1.2-V Switching Regulator (DC-DC)): Removed "Internal Switching Regulator Characteristics" table. Power efficiency is now listed in Section 5.6. ........................................................ 66 • Section 5.8.1.3 (Power Sequencing): Removed "Supply Ramp Rate" table. Supply ramp rate is now listed in Section 5.4. .......................................................................................................................... 68 • Section 5.8.1.4 (Power-On Reset (POR)): Updated section. ................................................................. 68 • Section 5.8.1.5 (Brownout Reset (BOR)): Added section. .................................................................... 68 • Table 5-19 (XCLKOUT Switching Characteristics): Moved f(XCO) parameter from Output Clock Frequency table to this table. Removed Output Clock Frequency table. ........................................................................... 75 • Section 5.8.3.3 (Input Clocks and PLLs): Updated description of the single-ended 3.3-V external clock. .............. 76 • Table 5-25 (Flash Parameters): Updated table. ................................................................................ 80 • Section 5.8.8 (Low-Power Modes): Removed STANDBY low-power mode. ............................................... 91 • Table 5-39 (Analog Pins and Internal Connections): Updated COMPARATOR SUBSYSTEM (MUX) columns. ..... 100 • Section 5.9.1.1.1 (Signal Mode): Added section. .............................................................................. 105 • Table 5-43 (ADC Characteristics): Updated MIN and MAX values of Gain Error (External reference). ............... 106 • Section 5.9.1.2.2 (ADC Timing Diagrams): Updated section. ............................................................... 111 • Table 5-46 (ADC Timing Parameters): Added table. ......................................................................... 112 • Section 5.9.2.1 (PGA Electrical Data and Timing): Added PGA Operating Conditions. ................................. 114 • Table 5-49 (PGA Characteristics): Updated table. ............................................................................ 114 • Section 5.9.2.1.1 (PGA Typical Characteristics Graphs): Added section. .................................................. 115 • Section 5.9.4 (Buffered Digital-to-Analog Converter (DAC)): Updated section. .......................................... 117 • Section 5.9.4.1 (Buffered DAC Electrical Data and Timing): Added Buffered DAC Operating Conditions. ........... 118 • Table 5-52 (Buffered DAC Electrical Characteristics): Updated table. ..................................................... 118 • Section 5.9.4.1.1 (Buffered DAC Illustrative Graphs): Added section. ..................................................... 119 • Section 5.9.4.1.2 (Buffered DAC Typical Characteristics Graphs): Added section. ...................................... 121 • Section 5.9.5.1.1 (CMPSS Illustrative Graphs): Added section. ............................................................ 126 • Table 5-63 (eQEP Timing Requirements): Changed "Synchronous" to "Asynchronous/Synchronous". ............... 143 • Table 5-63: Added footnote about limitations in the asynchronous mode. ................................................ 143 • Section 5.11.2.1 (I2C Electrical Data and Timing): Added NOTE about meeting I2C protocol timing specifications. 152 • Section 5.11.5.1.1 (Non-High-Speed Master Mode Timings): Updated parametric tables. ............................. 161 • Section 5.11.5.1.2 (Non-High-Speed Slave Mode Timings): Updated parametric tables. ............................... 164 • Section 5.11.5.1.3 (High-Speed Master Mode Timings): Updated parametric tables. ................................... 166 • Section 5.11.5.1.4 (High-Speed Slave Mode Timings): Updated parametric tables. .................................... 169 • Figure 5-83 (FSITX CPU Interface): Changed "VBUS" to "Register Interface". .......................................... 174 • Figure 5-84 (FSITX Block Diagram): Changed "VBUS Interface" to "Register Interface". .............................. 175 • Table 5-82 (FSITX Switching Characteristics): Updated table. ............................................................. 176 • Table 5-81 (FSITX GPIO Mux Groups): Added table. ....................................................................... 176 • Figure 5-85 (FSITX Timings): Updated figure. ................................................................................ 176 • Figure 5-86 (FSIRX CPU Interface): Changed "VBUS" to "Register Interface". .......................................... 177 • Figure 5-87 (FSIRX Block Diagram): Changed "VBUS Interface" to "Register Interface". .............................. 178 • Table 5-83 (FSIRX Timing Requirements): Updated table. ................................................................. 179 |
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