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US3881 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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6 / 6 page US3881 CMOS Low Voltage Hall Effect Latch 3901003881 Rev 4.2 7/23/01 Page 6 US3881 CMOS Low Voltage Hall Effect Latch Physical Characteristics U38 104 1 2 3 * All Dimensions in millimeters 2.13 1.87 0.45 0.41 Marked Surface 1.53 1.27 UA Hall Plate / Chip Location 1.60 1.40 45o Typical 4.30 3.90 2.64 2.34 0.84 0.63 3.20 2.80 1.75 1.55 0.48 0.43 0.20 0.00 0.41 0.35 1.30 1.24 2.57 2.51 5o Typical 45o Typical 0.38 Typical (see note 3) 15.5 14.5 0.41 0.35 UA Package Dimensions * MARKING: Line 1: 1st digit (U) = Supplier (Melexis) 2nd and 3rd digits (38) = Series (3880) Line 2: 1st digit (1) = Year (2001) 2nd and 3rd digits(04) = Week of Year PINOUT: Pin 1 V DD Pin 2 GND Pin 3 Output NOTES: 1.) Controlling dimension: mm 2.) Leads must be free of flash and plating voids 3.) Do not bend leads within 1mm of the lead to package interface. 4.) Package dimensions exclude molding flash 5.) Tolerance is 0.254mm unless otherwise specified SOT-23 Hall Plate / Chip Location (Bottom View) SOT-23 Package Dimensions (Top View) NOTES: 1. MARKING: 1st Digit (3) = Series (3881) 2nd Digit(1) = Year - 2001 Last Digits (04) = Week of Year 2. PINOUT (See Top View at left): Pin 1 VDD Pin 2 Output Pin 3 GND 3. Controlling dimension: mm. 4. Lead thickness after solder plating will be 0.254 mm maximum. 5. Package dimensions exclude molding flash. 6. The end flash shall not exceed 0.127 mm on each side of package. 7. Tolerance is +/- 0.254 mm unless otherwise specified. 1.55 1.45 0.95 0.85 3104 1.30 1.00 0.10 0.00 3.10 2.70 3.00 2.60 0.50 0.35 1.80 1.50 chip 0.66 0.56 0.20 MIN 0.25 0.10 2.10 1.70 0.90 0.70 * 1 2 3 Pin # For the latest version of this document, Go to our website at: WWW.melexis.com Or for additional information Contact Melexis Direct: Europe and Japan USA and rest of the world E-mail: sales_europe@melexis.com E-mail: sales_usa@melexis.com Phone: 011-32-13-670-780 Phone: (603)-223-2362 |
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