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AD673JD Datasheet(PDF) 7 Page - Analog Devices |
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AD673JD Datasheet(HTML) 7 Page - Analog Devices |
7 / 9 page AD673 REV. A –6– GROUNDING CONSIDERATIONS The AD673 provides separate Analog and Digital Common connections. The circuit will operate properly with as much as ±200 mV of common-mode voltage between the two commons. This permits more flexible control of system common bussing and digital and analog returns. In normal operation, the Analog Common terminal may gener- ate transient currents of up to 2 mA during a conversion. In ad- dition a static current of about 2 mA will flow into Analog Common in the unipolar mode after a conversion is complete. The Analog Common current will be modulated by the varia- tions in input signal. The absolute maximum voltage rating between the two com- mons is ±1 volt. It is recommended that a parallel pair of back-to-back protection diodes be connected between the commons if they are not connected locally. CONTROL AND TIMING OF THE AD673 The operation of the AD673 is controlled by two inputs: CON- VERT and DATA ENABLE. Starting a Conversion The conversion cycle is initiated by a positive-going CONVERT pulse at least 500 ns wide. The rising edge of this pulse resets the internal logic, clears the result of the previous conversion, and sets DR high. The falling edge of CONVERT begins the conversion cycle. When conversion is completed DR returns low. During the conversion cycle, DE should be held high. If DE goes low during a conversion, the data output buffers will be enabled and intermediate conversion results will be present on the data output pins. This may cause bus conflicts if other de- vices in a system are trying to use the bus. tCS tDSC VOH + VOL 2 VIH + VIL 2 tC CONVERT DR Figure 9. Convert Timing Reading the Data The three-state data output buffers is enabled by DE. Access time of these buffers is typically 150 ns (250 maximum). The Data outputs remain valid until 50 ns after the enable signal re- turns high, and are completely into the high-impedance state 100 ns later. VIH + VIL 2 DE tHD tDD VOH VOL DATA VALID tHL HIGH IMPEDANCE HIGH IMPEDANCE DB0–DB7 Figure 10. Read Timing TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Units CONVERT Pulse Width tCS 500 — — ns DR Delay from CONVERT tDSC — 1 1.5 µs Conversion Time tC 10 20 30 µs Data Access Time tDD 0 150 250 ns Data Valid after DE High tHD 50 — — ns Output Float Delay tHL — 100 200 ns MICROPROCESSOR INTERFACE CONSIDERATIONS— GENERAL When an analog-to-digital converter like the AD673 is inter- faced to a microprocessor, several details of the interface must be considered. First, a signal to start the converter must be gen- erated; then an appropriate delay period must be allowed to pass before valid conversion data may be read. In most applications, the AD673 can interface to a microprocessor system with little or no external logic. The most popular control signal configuration consists of de- coding the address assigned to the AD673, then gating this sig- nal with the system’s WR signal to generate the CONVERT pulse, and gating it with RD to enable the output buffers. The use of a memory address and memory WR and RD signals de- notes “memory-mapped” I/O interfacing, while the use of a separate I/O address space denotes “isolated I/O” interfacing. Figure 11 shows a generalized diagram of the control logic for an AD673 interfaced to an 8-bit data bus, where an address ADC ADDR has been decoded. ADC ADDR starts the con- verter when written to (the actual data being written to the con- verter does not matter) and contains the high byte data during read operations. Figure 11. General AD673 Interface to 8-Bit Microprocessor |
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