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SLG46532 Datasheet(PDF) 93 Page - Dialog Semiconductor |
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SLG46532 Datasheet(HTML) 93 Page - Dialog Semiconductor |
93 / 184 page SLG46532_DS_108 Page 92 of 183 SLG46532 9.9 Wake and Sleep controller (WS) The SLG46532 has a Wake and Sleep function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this purpose reg<1319:1318>=11 and reg<1495>=1. The WS serves for power saving, it allows to switch on and off selected ACMPs on selected bit of 16-bit counter. To use any ACMP under WS controller the following settings must be done: • ACMP Power Up Input from matrix = 1 (for each ACMP separately) • CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs) • Register WS => enable (for each ACMP separately) • CNT/DLY0 set/reset input = 0 (for all ACMPs) As the OSC any oscillator with any pre divider can be used. The user can select a period of time while the ACMPs are sleeping in a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched so the ACMPs remain their state (High or Low) while sleeping. WS controller has the following settings: • Wake and Sleep Output State (High/Low) If OSC is powered off (Power Down option is selected; power down input = 1) and Wake and Sleep Output State = High, the ACMP is continuously on Figure 37. WS controller OSC CK_OSC WS_PD 000:/1 001:/4 010:/12 011:/24 100:/64 cnt_end WS out WS_PD Power Control From Connection Matrix Output<58> Analog Control Block reg<1316:1314> WS_PD to W&S out state selection block WS clock freq. selection reg<1591:1576> WS ratio control data reg<1494> WS out state for OSC off ACMPs_pdb WS out bg/regulator pdb WS time selection reg<1489> ACMP0..3 OUT To Connection Matrix Input <60:57> From Connection Matrix Output <54:51> reg<1493:1490> ACMP WS enable WS out Latchs Note: WS_PD is High at WS OSC (25 KHz/2MHz OSC) power down WS Controller CNT0 out To Connection Matrix Input <22> ck CNT 4 4 4 4 4 ACMPs_pdb + - |
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