TB1261F datasheet(9/66 Pages) TOSHIBA

Part #	TB1261F

Description	TOSHIBA BiCMOS INTEGRATED CIRCUIT, SILICON MONOLITHIC

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Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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9 / 66 page

TB1261F/TB1262F

2002-6-30 9 / 66

#

Description

35

(31)

DIG. VDD ;

A Vdd terminal for of digital block. Supply

HVcc voltage through 270 ohms of resistance.

The coupling capacitor should be 10uF or less,

in order to keep rise up time good enough.

The voltage of this terminal is clipped to

approximately 3.3V by the internal regulator.

36

QFP

only

Da

Dac2;

c2;

A terminal to be output High/ Low status by an

open collector interface. The pull up resistance

should be fixed as a sink current is 1mA or less

and the voltage is less than the voltage of H

Vcc.

37

(32)

FBP IN;

An input terminal for FBP. V/GP pulses are

output over this FBP.

The Threshold levels are;

1.4 V ;

for Blanking

3.7 V;

for HAFC2

38

nc;

39

(33)

H OUT;

An output terminal for horizontal driving

pulses.;

40

QFP

only

VD OUT;

An output terminal for VD pulses. The pulses

are 3V for its level.

41

QFP

only

HD OUT;

An output terminal fot HD pulses. GP Pulses

are overlaid as SCP.

Also BPP is overlaid to stop black stretch

detecting.

Those levels are

5V;

for GP out

3V;

for HD out

0.7V;

for BPP in

42

QFP

only

Sync out;

An output terminal of the sliced sync pulses.

Pull up this pin with 5.1kΩ of resistance.

43

(34)

H AFC

H AFC F

F

Filter

ilter

ilter;;;;

A terminal should be connected with H. AFC

Filter. The DC voltage of this pin controls the H

VCO frequency.

44

QFP

only

Y3/CVBS3 IN;

An alternative input terminal for;

-

Y + Sync signals of Y/Cb/Cr_3

-

Or CVBS_3

Those two are selected by IICBUS

This terminal is clamped by charging /

discharging the coupling capacitors. It is

recommended that input impedance is kept at

or below 100Ω. Input level 1Vp-p/140IRE

45

(35)

H VCC (9V);

A Vcc terminal for DEF circuit, HOUT, IICBUS

POR, etc. Supply 9V.;

#

Description

46

(36)

V RAMP;

A terminal should be connected with a capacitor

to generate the V.Ramp signal.Connect this pin

to GND via 0.47uF.The V.Ramp amplitude is

kept constant by the V.AGC.;

47

(37)

V OUT;

An output terminal for the vertical saw tooth

wave.

48

49

QFP

only

Cb3 IN;

Cr3 IN;

Input terminals for ;

-

Cb and Cr signals of Y/Cb/Cr_3

These terminals are clamped by charging /

discharging the coupling capacitors. It is

recommended that input impedance is kept at

or below 100Ω.

50

(38)

DIG GND;

A GND terminal for digital block.;

51

52

(39)

(40)

Cr OUT;

Cb OUT;

Output terminals for demodulated Cb and Cr

signals.

53

(41)

Y/Mon OUT

An alternative output terminal for;

-

Y signal after Y1 process

-

Or Mon out after selector

Those two are selected by IICBUS

54

(42)

BLACK DET;

A terminal should be connected with Black

level detecting filter for black stretch. This

terminal voltage controls the Black stretching

gain. The IIC Bus controls the on/off and start

point of the Black stretch. ;

55

(43)

Y2/CVBS2/G IN

An alternative input terminal for;

-

Y + Sync signals of Y/Cb/Cr_2 in

-

Or CVBS_2

-

Or G signal of Scart Y/R/G/B in

Those three are selected by IICBUS.

These terminals are clamped by charging /

discharging the coupling capacitors. It is

recommended that input impedance is kept at

or below 100Ω.

56

57

(44)

(45)

Cb2/B IN;

Cr2/R IN;

Alternative input terminals for;

-

Cb and Cr signals of Y/Cb/Cr_2

-

Or R and B signal of Scart Y/R/G/B in

Those three are selected by IICBUS

These terminals are clamped by charging /

discharging the coupling capacitors. It is

recommended that input impedance is kept at

or below 100Ω.

58

(46)

C

C----IN;

IN;

An input terminal for chroma signal (standard

burst amplitude level 286mVp-p). The dc level

of this pin can be read by bus to detect if S port

is connected or not.;

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