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STK25CA8 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. STK25CA8
Description  128K x 8 AutoStore nvSRAM CMOS Nonvolatile Static RAM Module
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Maker  ETC [List of Unclassifed Manufacturers]
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STK25CA8 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

   
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STK25CA8
August 1999
6-3
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
Note f:
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g:
I/O state assumes E, G, < VIL and W > VIH; device is continuously selected.
Note h:
Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
SRAM READ CYCLE #2: E Controlledf
NO.
SYMBOLS
PARAMETER
STK25CA8-35
STK25CA8-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1tELQV
tACS
Chip Enable Access Time
35
45
ns
2tAVAV
f
tRC
Read Cycle Time
35
45
ns
3tAVQV
g
tAA
Address Access Time
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
15
20
ns
5tAXQX
g
tOH
Output Hold after Address Change
5
5
ns
6tELQX
tLZ
Chip Enable to Output Active
5
5
ns
7tEHQZ
h
tHZ
Chip Disable to Output Inactive
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
ns
9tGHQZ
h
tOHZ
Output Disable to Output Inactive
13
15
ns
10
tELICCH
e
tPA
Chip Enable to Power Active
0
0
ns
11
tEHICCL
d, e
tPS
Chip Disable to Power Standby
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ


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