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DA9063L Datasheet(PDF) 72 Page - Dialog Semiconductor |
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DA9063L Datasheet(HTML) 72 Page - Dialog Semiconductor |
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72 / 173 page  DA9063L System PMIC for Mobile and Automotive Applications Datasheet DA9063L_2v1 05-Apr-2017 CFR0011-120-00 72 of 173 © 2017 Dialog Semiconductor 6.8.1.1 Details of the 2-wire control bus protocol All data is transmitted across the 2-bus in groups of 8 bits. To send a bit, the DATA line is driven at the intended state while the CLK is LOW (a low on DATA indicates a zero bit). Once the DATA has settled, the CLK line is brought high and then low. This pulse on CLK clocks the DATA bit into the receiver’s shift register, see Figure 19. A two byte serial protocol is used containing one byte for address and one byte data. Data and address transfer is MSB transmitted first for both read and write operations. Transmission begins with the START condition from the master while the bus is idle. It is initiated by a high-to-low transition on the DATA line while the CLK is in the high state (a STOP condition is indicated by a low- to-high transition on the DATA line while the CLK is in the high state). CLK DATA Figure 19: Timing of START and STOP Condition The 2-WIRE bus is monitored by the DA9063L for a valid slave address when the interface is enabled. It responds immediately when it receives its own slave address. This ‘Acknowledge’ is done by pulling the DATA line low during the following clock cycle (see the white blocks marked A in Figure 20 to Figure 24). The protocol for a register write from master to slave consists of a start condition, a slave address with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP condition (all bytes responded by DA9063L with Acknowledge), as illustrated in Figure 20. S SLAVEadr REGadr A A DATA A P W S = START condition P = STOP condition Slave to master A = Acknowledge (low) W = Write (low) Master to slave 7 bits 1 bit 8 bits 8 bits Figure 20: Byte Write (DATA Line) When the host reads data from a register, it first has to write access the DA9063L with the target register address and then read access the DA9063L with a Repeated START or alternatively a second START condition. After receiving the data, the host sends Not Acknowledge and terminates the transmission with a STOP condition (Figure 21). S = START condition Sr = Repeated START condition P = STOP condition Slave to master A = Acknowledge (low) A* = No Acknowledge W = Write (low) Master to slave S SLAVEadr A DATA A* P W 7 bits 1 bit 8 bits A R S SLAVEadr 7 bits 1 bit REGadr A 8 bits R = Read (high) S SLAVEadr A DATA A* P W 7 bits 1 bit 8 bits A R Sr SLAVEadr 7 bits 1 bit REGadr A 8 bits P Figure 21: Examples of Byte Read (DATA Line) |
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