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TPS65321A-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65321A-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 43 page  6 TPS65321A-Q1 SLVSE55 – NOVEMBER 2017 www.ti.com Product Folder Links: TPS65321A-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.5 Electrical Characteristics VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating junction temperature TJ = –150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN (INPUT POWER SUPPLY) Operating input voltage Normal mode, after initial start-up 3.6 12 36 V Shutdown supply current V(EN1) = V(EN2) = 0 V, 25°C 2 7 μA Initial start-up voltage 6 36 V ENABLE AND UVLO (EN1 AND EN2 PINS) Enable low level 0.7 V Enable high level 2.5 V V(VIN)(f) Internal UVLO falling threshold Ramp V(VIN) down until output turns OFF 1.8 2.6 3 V V(VIN)(r) Internal UVLO rising threshold Ramp V(VIN) up until output turns ON 2.2 2.8 3.2 V BUCK REGULATOR I(Qon) Operating: non-switching supply Measured at the VIN pin V(FB1) = 0.83 V, V(VIN) = 12 V, 25°C 110 140 μA Output capacitance ESR = 0.001 Ω to 0.1 Ω, large output capacitance may be required for load transient 10 μF V(ref1) Voltage reference for FB1 pin Buck regulator output: 1.1 V to 20 V. Buck regulator in Continuous Conducting Mode without Pulse-Skipping 0.788 0.8 0.812 V DC output voltage accuracy Includes voltage references, DC load and line regulation, process and temperature -2 2 % DC(LDR) DC Load regulation, ΔVOUT / VOUT IOUT = 0 to IOUTmax 0.5 % T(LDSR) Transient load step response V(VIN) = 12V, IOUT = 200 mA to 3A, TR = TF = 1 µs, Buck Output Voltage = 5V, ƒS = 2 MHz 5 % BUCK REGULATOR: HIGH-SIDE MOSFET r(DS(on) HS FET) On-resistance V(VIN) = 12 V, V(SW) = 6 V 127 250 m Ω tonmin Minimum on-time ƒS = 2.5 MHz 115 ns BUCK REGULATOR: CURRENT-LIMIT Current-limit threshold V(VIN) = 12 V, TJ = 25°C 4 6 A BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) ƒS Switching-frequency range Under RT mode 100 2500 kHz Under fixed-frequency PWM mode, with 200 kΩ connected between RT/CLK and GND pins 523 585 640 kHz Under CLK mode 300 2200 kHz Minimum CLK input pulse width Measures at CLK input = 2.2 MHz 30 ns RT/CLK High threshold 1.9 2.2 V RT/CLK Low threshold 0.5 0.7 V RT/CLK Falling edge to SW rising edge delay Measured at 500 kHz with external clock connected to RT/CLK pin 60 ns PLL Lock-in time Measured at 500 kHz 100 μs BUCK REGULATOR: INTERNAL SOFT START TIMER IDischarge(SS) Soft-start Pin Discharge Current V(SS) = 1 V, EN1=0, TA = 25°C 50 400 μA V(SS) = 1 V, EN1=0, TA = 125°C 33 400 μA LDO REGULATOR ΔVO(ΔVI) Line regulation V(VIN_LDO) = 6 V to 30 V, I(LDO_OUT) = 10 mA, V(LDO_OUT) = 3.3 V 20 mV |
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