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## TPS65321A-Q1 Datasheet(PDF) 28 Page - Texas Instruments

 Part # TPS65321A-Q1 Description 36-V Step-Down Converter With Eco-mode and LDO Regulator Download 43 Pages Scroll/Zoom 100% Manufacturer TI1 [Texas Instruments] Direct Link http://www.ti.com Logo

## TPS65321A-Q1 Datasheet(HTML) 28 Page - Texas Instruments

 28 / 43 pageS1C2πR3ƒ=´´OESRCRC2R3´=P _ mod1C12πR3ƒ=´´28TPS65321A-Q1SLVSE55 – NOVEMBER 2017www.ti.comProduct Folder Links: TPS65321A-Q1Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated(39)Equation 37 yields 4.69 nF for compensating capacitor C1 (see the schematic in Figure 16). For this design,select a value of 4.7 nF for C1.To implement a compensation pole as needed, use an additional capacitor, C2, in parallel with the seriescombination of R3 and C1. Use Equation 40 and Equation 41 to calculate the value of C2 and select the largerresulting value to set the compensation pole. Type 2B compensation does not use C2 because it would demanda low ESR of the output capacitor.(40)(41)8.2.1.2.10LDO RegulatorDepending on the end application, use different values of external components can be used. To program theoutput voltage, carefully select the feedback resistors, R5 and R6 (see the schematic in Figure 16). Using smallerresistors results in higher current consumption, whereas using very large resistors impacts the sensitivity of theregulator. Therefore selecting feedback resistors such that the sum of R5 and R6 is between 20 kΩ and 200 kΩis recommended.If the desired regulated output voltage is 5 V on selecting R6, the value of R5 can be calculated. With Vref = 0.8 V(typical), VO = 5 V, and selecting R6 = 18 kΩ, the calculated value of R5 is 95.3 kΩ.An output capacitor for the LDO regulator is required (see C10 in Figure 16) to prevent the output fromtemporarily dropping down during fast load steps. TI recommends a low-ESR ceramic capacitor with dielectric oftype X5R or X7R. Additionally, a bypass capacitor can be connected at the output to decouple high-frequencynoise based on the requirements of the end application.8.2.1.2.11Power Dissipation8.2.1.2.11.1Power Dissipation Losses of the Buck RegulatorUse the following equations to calculate the power dissipation losses for the buck regulator. These losses areapplicable for continuous-conduction-mode (CCM) operation.1. Conduction loss:PCON = IO2 × rDS(on) × (VO / VI)where•IO is the buck regulator output current•VO is the buck regulator output voltage•VI is the input voltage(42)2. Switching loss:PSW = ½ × VI × IO × (tr + tf) × fSwhere•tr is the FET switching rise time (tr maximum = 20 ns)•tf is the FET switching fall time (tf maximum = 20 ns)•ƒS is the switching frequency of the buck regulator(43)3. Gate drive loss:PGate = Vdrive × Qg × ƒswwhere•Vdrive is the FET gate-drive voltage (typically Vdrive = 6 V)•Qg = 1 × 10–9 (nC, typical)(44)

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