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TPS65321AQ1 Datasheet(PDF) 27 Page  Texas Instruments 


TPS65321AQ1 Datasheet(HTML) 27 Page  Texas Instruments 
27 / 43 page CO O O ps ref ea 2π ƒ C V R3 gm V gm æ ö æ ö ´ ´ = ´ ç ÷ ç ÷ ç ÷ ´ è ø è ø S CO P _ mod ƒ ƒ ƒ 2 = ´ CO P _ mod Z _ mod ƒ ƒ ƒ = ´ Z _ mod ESR O 1 ƒ 2π R C = ´ ´ m ax P _ mod L O O O I 1 ƒ 2π R C 2π V C = = ´ ´ ´ ´ 27 TPS65321AQ1 www.ti.com SLVSE55 – NOVEMBER 2017 Product Folder Links: TPS65321AQ1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated When the softstart time is known, use Equation 2 to calculate the softstart capacitor. For the example circuit, the softstart time is not too critical because the outputcapacitor value is 2 × 47 µF, which does not require much current to charge to 3.3 V. The example circuit has the softstart time set to an arbitrary value of 1 ms, which requires a 3.125 nF softstart capacitor. This design uses the nextlarger standard value of 3.3 nF. 8.2.1.2.7 Bootstrap Capacitor Selection for the Buck Regulator Connect a 0.1µF ceramic capacitor between the BOOT and SW pins for proper operation. TI recommends using a ceramic capacitor with X5R or bettergrade dielectric. The capacitor should have a 10V or higher voltage rating. 8.2.1.2.8 Output Voltage and Feedback Resistor Selection for the Buck Regulator The voltage divider of R1 and R2 sets the output voltage. For the design example, the selected value of R2 is 10 k Ω, and the calculated value of R1 is 32.1 kΩ. Because of current leakage of the FB1 pin, the current flowing through the feedback network should be greater than 1 μA to maintain the outputvoltage accuracy. Selecting higher resistor values decreases the quiescent current and improves efficiency at low output currents, but can introduce noise immunity problems. 8.2.1.2.9 Frequency Compensation Selection for the Buck Regulator Several possible methods exist to design closed loop compensation for DCDC converters. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the buck regulator. Ignoring the slope compensation usually causes the actual crossover frequency to be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero, and that the ESR zero is at least 10 times greater than the modulator pole. To begin, use Equation 34 to calculate the modulator pole, ƒP_mod, and Equation 35 to calculate the ESR zero, ƒz_mod. (34) (35) Use Equation 36 and Equation 37 to calculate an estimate starting point for the crossover frequency, ƒCO, to design the compensation. (36) (37) For the example design, ƒP_mod is 1.54 kHz and ƒZ_mod is 564 kHz. Equation 36 is the geometric mean of the modulator pole and the ESR zero and Equation 37 is the mean of the modulator pole and the switching frequency. Equation 36 yields 29.5 kHz and Equation 37 results 41.1 kHz. Use the lower value of Equation 36 or Equation 37 for an initial crossover frequency. For this example, the target ƒCO value is 29.5 kHz. Next, calculate the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. The total loop gain, which consists of the product of the modulator gain, the feedback voltagedivider gain, and the error amplifier gain at ƒCO equal to 1. Use Equation 38 to calculate the compensation resistor, R3 (see the schematic in Figure 16). (38) Assume the powerstage transconductance, gmps, is 10.5 S. The output voltage (VO), reference voltage (Vref), and amplifier transconductance, (gmea) are 3.3 V, 0.8 V, and 310 μS, respectively. The calculated value for R3 is 22.1 k Ω. For this design, use a value of 22 kΩ for R3. Use Equation 39 to set the compensation zero to the modulator pole frequency. 
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