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SN74ALS166 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN74ALS166
Description  PARALLEL-LOAD 8-BIT SHIFT REGISTER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74ALS166 Datasheet(HTML) 1 Page - Texas Instruments

 
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SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156D – APRIL 1982 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Synchronous Load
D Direct Overriding Clear
D Parallel-to-Serial Conversion
D Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages and Standard Plastic (N) DIP
description
The SN74ALS166 parallel-load 8-bit shift register
is compatible with most other TTL logic families.
All inputs are buffered to lower the drive
requirements. Input clamping diodes minimize
switching transients and simplify system design.
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They
feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in
modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input
and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data
(A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial
data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a
two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the
system clock to be free running and the register can be stopped on command with the clock input. CLK INH
should be changed to the high level only when CLK is high. The buffered CLR overrides all other inputs, including
CLK, and sets all flip-flops to zero.
The SN74ALS166 is characterized for operation from 0
°C to 70°C.
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUT
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
OUTPUTS
OUTPUT
QH
CLR
SH/LD
CLK INH
CLK
SER
A...H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
XL
L
X
X
QA0
QB0
QH0
H
LL
X
a ...h
a
bh
H
HL
HX
H
QAn
QGn
H
HL
LX
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
© 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
D, DB, OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SER
A
B
C
D
CLK INH
CLK
GND
VCC
SH/LD
H
QH
G
F
E
CLR


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