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NCP81243 Datasheet(PDF) 24 Page - ON Semiconductor |
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NCP81243 Datasheet(HTML) 24 Page - ON Semiconductor |
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24 / 26 page  NCP81243 www.onsemi.com 24 Over Current Latch−Off Protection The NCP81243 compares a programmable current−limit set point to the voltage from the output of the current−summing amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current ICL. If the current generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (ICL), an internal latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150% load current) after which the outputs will remain disabled until the Vcc voltage or EN is toggled. The voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current balance circuitry. An inherent per−phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equations. Equation related to the NCP81243: R ILIM + I LIM @ DCR @ R CS R PH I CL Where ICL = 10 mA R PH R CS RLIM ILIM CSCOMP CSSUM R PH R PH CSREF Input Under–Voltage Lockouts NCP81243 monitors the 5 V VCC supply as well as the VRMP pin. Hysteresis is incorporated within these comparators. If either the Vcc or the VRMP UVLO requirements are not met the VR will fail to startup and the Intel proprietary interface interface will be unresponsive to all commands. Under Voltage Monitor The output voltage is monitored at the output of each differential amplifier for UVLO. If the output falls more than 300 mV below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low. Over Voltage Protection The output voltage for each rail is also monitored for OVP at the output of the differential amplifier and also at the CSREF pin. During normal operation, if the output voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the output voltage will be ramped down to 0 V, the ramp to 0 V is controlled to avoid producing negative output voltage. At the same time, the PWMs of the OVP rail are sent low. The PWM outputs will pulse to mid level during the DAC ramp down period if the output decreases below the DAC+OVP threshold as DAC decreases. When the DAC reaches 0 V, the PWMs will be held low, the high side gate drivers are all turned off and the low side gate drivers are all turned on. The part will stay in this mode until the Vcc voltage or EN is toggled. |
Similar Part No. - NCP81243_17 |
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Similar Description - NCP81243_17 |
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