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NCP81243 Datasheet(PDF) 23 Page - ON Semiconductor

Part # NCP81243
Description  Dual Output 3 & 2 Phase Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP81243 Datasheet(HTML) 23 Page - ON Semiconductor

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NCP81243
www.onsemi.com
23
Protection Features
Under Voltage Lockouts
There are several under voltage monitors in the system.
Hysteresis
is
incorporated
within
the
comparators.
NCP81243 monitors the 5 V VCC supply. The gate driver
monitors both the gate driver VCC and the BST voltage.
When the voltage on the gate driver is insufficient it will pull
DRON low and prevents the controller from being enabled.
The gate driver will hold DRON low for a minimum period
of time to allow the controller to hold off it’s startup
sequence. In this case the PWM is set to the MID state to
begin soft start.
DAC
Gate Driver Pulls DRON
Low during driver UVLO
and Calibration
If DRON is pulled low the
controller will hold off its
startup
Figure 8. Gate Driver UVLO Restart
Start Up Sequence
Following the rise of Vcc and VRMP above the UVLO
thresholds, externally programmed data is collected. After
the configuration data is collected, the PWMs will be set to
2.0 V MID state to indicate that the drivers should be in
diode mode. When the device is enabled DRON will then be
asserted high to activate the gates, please note that there is
only one Enable pin, once this enable is pulled high both the
main and Auxiliary rail is enabled at this time. A digital
counter steps the DAC up from Zero to the target voltage
level based on the soft start slew rate selected. As the DAC
ramps the PWM outputs for each rail will begin to fire. Each
phase will move out of the MID state when the first PWM
pulse is produced. When the controller is disabled the PWM
signal will return to the MID state. When the controller is
disabled, the PWM signals will return to Mid – level.
Figure 9. Startup Operation


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