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FDMF6705 Datasheet(PDF) 14 Page - ON Semiconductor

Part No. FDMF6705
Description  Extra-Small, High-Performance, High-Frequency DrMOS Module
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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FDMF6705 Datasheet(HTML) 14 Page - ON Semiconductor

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© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FDMF6705 • Rev. 1.0.4
13
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time while eliminating potential shoot
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 26
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 begins to turn off after some propagation
delay (tPD_PHGLL). Once the GL pin is discharged below
~1 V, Q1 begins to turn on after adaptive delay
tD_DEADON. To preclude overlap during the HIGH-to-LOW
transition (Q1 off to Q2 on), the adaptive circuitry
monitors the voltage at the VSWH pin. When the PWM
signal goes LOW, Q1 begins to turn off after some
propagation delay (tPD_PLGHL). Once the VSWH pin falls
below ~2.2 V, Q2 begins to turn on after adaptive delay
tD_DEADOFF. Additionally, VGS(Q1) is monitored. When
VGS(Q1) is discharged below ~1.2 V, a secondary
adaptive delay is initiated, which results in Q2 being
driven on after tD_TIMEOUT, regardless of SW state. This
function is implemented to ensure CBOOT is recharged
each switching cycle in the event that the SW voltage
does not fall below the 2.2 V adaptive threshold.
Secondary delay tD_TIMEOUT is longer than tD_DEADOFF.
Figure 26. PWM and 3-StateTiming Diagram
Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal.
Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
PWM
Exiting 3-state
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
SMOD#
Dead Times
tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS
tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
tPD_TSGHH
VSWH
GH
to
VSWH
GL
tPD_PHGLL
tD_HOLD -OFF
90%
less than
tD_HOLD -OFF
Exit
3 State
1.0V
PWM
VIL_PWM
VIH_PWM
VTRI_HI
VIH_PWM
VIH_PWM
10%
tR_GL
tD_HOLD -OFF
tPD_TSGLH
less than
tD_HOLD -OFF
Exit
3-State
V
IH PWM
VTRI_HI
VTRI_LO
VIL_PWM
t
PD_PLGHL
tPD_TSGHH
DCM
tF_GH
tR_GH
tD_HOLD-OFF
10%
CCM
DCM
Exit
3-State
90%
10%
90%
Enter
3 -State
Enter
3 -State
tD_DEADOFF
tD_DEADON
Enter
3-State
tF_GL
VIN
VOUT
2.2V


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