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FDMF6705 Datasheet(PDF) 13 Page - ON Semiconductor

Part No. FDMF6705
Description  Extra-Small, High-Performance, High-Frequency DrMOS Module
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

FDMF6705 Datasheet(HTML) 13 Page - ON Semiconductor

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© 2011 Fairchild Semiconductor Corporation
FDMF6705 • Rev. 1.0.4
Functional Description
The FDMF6705 is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable
The VCIN pin is monitored by an under-voltage lockout
(UVLO) circuit. When VCIN rises above ~3.1 V, the driver
is enabled for operation. When VCIN falls below ~2.7 V,
the driver is disabled (GH, GL=0). The driver can also
be disabled by pulling the DISB# pin LOW (DISB# <
VIL_DISB), which holds both GL and GH LOW regardless
of the PWM input state. The driver can be enabled by
raising the DISB# pin voltage HIGH (DISB# > VIH_DISB).
Table 1.
UVLO and Disable Logic
Driver State
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Enabled (See Table 2)
Disabled (GH, GL=0)
DISB# has an internal pull-down current source of
10 µA.
Thermal Warning Flag
The FDMF6705 provides a thermal warning flag
(THWN) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN output
requires a pull-up resistor, which can be connected to
VCIN. THWN does NOT disable the DrMOS module.
Figure 25. THWN Operation
3-State PWM Input
The FDMF6705 incorporates a 3-state PWM input gate
drive design. The 3-state gate drive has both logic HIGH
level and LOW level, along with a 3-state shutdown
window. When the PWM input signal enters and
remains within the 3-state window for a defined hold-off
time (tD_HOLD-OFF), both GL and GH are pulled LOW. This
feature enables the gate drive to shut down both high-
and low-side MOSFETs to support features such as
phase shedding, which is a common feature on
multiphase voltage regulators.
Operation when Exiting 3-State Condition
When exiting a valid 3-state condition, the FDMF6705
design follows the PWM input command. If the PWM
input goes from 3-state to LOW, the low side MOSFET
is turned on. If the PWM input goes from 3-state to
HIGH, the high-side MOSFET is turned on. This is
illustrated in Figure 26. The FDMF6705 design allows
for short propagation delays when exiting the 3-state
window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced low RDS(ON) N-channel MOSFET. The bias
for GL is internally connected between VDRV and
CGND. When the driver is enabled, the driver's output is
180° out of phase with the PWM input. When the driver
is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driver is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, VSWH is
held at PGND, allowing CBOOT to charge to VDRV
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET (Q1). During this transition, the charge is
removed from CBOOT and delivered to the gate of Q1. As
Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to
VIN + VBOOT, which provides sufficient VGS enhancement
for Q1. To complete the switching cycle, Q1 is turned off
by pulling GH to VSWH. CBOOT is then recharged to
VDRV when VSWH falls to PGND. GH output is in-
phase with the PWM input. The high-side gate is held
LOW when the driver is disabled or the PWM signal is
held within the 3-state window for longer than the 3-
state hold-off time, tD_HOLD-OFF.

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